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1. 发明申请

US20190095350A1 System, Apparatus And Method For Page Granular,Software Controlled Multiple Key Memory Encryption 审中-公开
公开(公告)号：US20190095350A1
公开(公告)日：2019-03-28
申请号：US15714217
申请日：2017-09-25
申请人： David M. Durham , Siddhartha Chhabra , Amy L. Santoni , Gilbert Neiger , Barry E. Huntley , Hormuzd M. Khosravi , Baiju V. Patel , Ravi L. Sahita , Gideon Gerzon , Ido Ouziel , Ioannis T. Schoinas , Rajesh M. Sankaran
发明人： David M. Durham , Siddhartha Chhabra , Amy L. Santoni , Gilbert Neiger , Barry E. Huntley , Hormuzd M. Khosravi , Baiju V. Patel , Ravi L. Sahita , Gideon Gerzon , Ido Ouziel , Ioannis T. Schoinas , Rajesh M. Sankaran
IPC分类号： G06F12/14 , G06F21/60 , G06F21/82 , G06F3/06
摘要： In one embodiment, a cryptographic circuit is adapted to receive a data line including at least an encrypted portion from a memory in response to a read request having a memory address from a first agent, obtain a key identifier for a key of the first agent from the data line, obtain the key using the key identifier, decrypt the at least encrypted portion of the data line using the key and send decrypted data of the at least encrypted portion of the data line to the first agent. Other embodiments are described and claimed.

2. 发明申请

US20160094552A1 CREATING STACK POSITION DEPENDENT CRYPTOGRAPHIC RETURN ADDRESS TO MITIGATE RETURN ORIENTED PROGRAMMING ATTACKS 有权
标题翻译：创建堆栈位置相关的CRYPTOGRAPHIC返回地址以减轻面向方面的编程攻击
公开(公告)号：US20160094552A1
公开(公告)日：2016-03-31
申请号：US14498521
申请日：2014-09-26
申请人： David M. Durham , Baiju V. Patel
发明人： David M. Durham , Baiju V. Patel
IPC分类号： H04L29/06
CPC分类号： G06F21/00 , G06F21/52
摘要： A computing device includes technologies for securing return addresses that are used by a processor to control the flow of execution of a program. The computing device uses a cryptographic algorithm to provide security for a return address in a manner that binds the return address to a location in a stack.
摘要翻译：计算设备包括用于保护由处理器使用以控制程序的执行流程的返回地址的技术。计算设备使用加密算法以将返回地址绑定到堆栈中的位置的方式为返回地址提供安全性。

3. 发明授权

US08719819B2 Mechanism for instruction set based thread execution on a plurality of instruction sequencers 有权
标题翻译：基于多个指令定序器的基于指令集的线程执行的机制
公开(公告)号：US08719819B2
公开(公告)日：2014-05-06
申请号：US11173326
申请日：2005-06-30
申请人： Hong Wang , John Shen , Ed Grochowski , James Paul Held , Bryant Bigbee , Shivnandan D. Kaushik , Gautham Chinya , Xiang Zou , Per Hammarlund , Xinmin Tian , Anil Aggarwal , Scott Dion Rodgers , Prashant Sethi , Baiju V. Patel , Richard Andrew Hankins
发明人： Hong Wang , John Shen , Ed Grochowski , James Paul Held , Bryant Bigbee , Shivnandan D. Kaushik , Gautham Chinya , Xiang Zou , Per Hammarlund , Xinmin Tian , Anil Aggarwal , Scott Dion Rodgers , Prashant Sethi , Baiju V. Patel , Richard Andrew Hankins
IPC分类号： G06F9/46
CPC分类号： G06F9/3867 , G06F9/30003 , G06F9/30043 , G06F9/3005 , G06F9/3009 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/3851 , G06F9/4843 , G06F9/4881
摘要： In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
摘要翻译：在一个实施例中，提供了一种方法。该方法包括响应于在应用级程序的控制下对第二指令定序器执行用户级指令来管理第一指令定序器上的用户级线程。在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。第一用户级指令至少具有1）引用一个或多个指令定序器的字段，或者2）使用指向代码执行代码时特定寻址一个或多个指令定序器的代码的指针进行隐式引用。

4. 发明授权

US08689215B2 Structured exception handling for application-managed thread units 有权
标题翻译：应用程序管理的线程单元的结构化异常处理
公开(公告)号：US08689215B2
公开(公告)日：2014-04-01
申请号：US11642384
申请日：2006-12-19
申请人： Richard A. Hankins , Gautham N. Chinya , Hong Wang , David K. Poulsen , Shirish Aundhe , Baiju V. Patel , Sanjiv M. Shah
发明人： Richard A. Hankins , Gautham N. Chinya , Hong Wang , David K. Poulsen , Shirish Aundhe , Baiju V. Patel , Sanjiv M. Shah
IPC分类号： G06F9/46
CPC分类号： G06F9/4812 , G06F9/3851 , G06F9/3861
摘要： Methods, data structures, instructions, and techniques for structured exception handling for user-level threads in a multi-threading system are provided. Registered filter routines may be dispatched to a thread unit not managed by the operating system (OS). The dispatch may occur by allowing an OS-managed thread unit (proxy) to invoke the OS-provided structured exception handling service (including dispatcher) on behalf of the sequestered thread unit. Alternatively, an OS-managed thread unit may include dispatch code and may, without OS intervention, dispatch the filter routine to the sequestered thread unit. Other embodiments are also described and claimed.
摘要翻译：提供了用于多线程系统中的用户级线程的结构化异常处理的方法，数据结构，指令和技术。注册的过滤器例程可以被分派到不由操作系统（OS）管理的线程单元。调度可以通过允许OS管理的线程单元（代理）代表被隔离的线程单元来调用OS提供的结构化异常处理服务（包括调度程序）。或者，OS管理的线程单元可以包括调度代码，并且可以在没有OS干预的情况下将过滤器例程分派到隔离的线程单元。还描述和要求保护其他实施例。

5. 发明申请

US20130219154A1 CONTEXT STATE MANAGEMENT FOR PROCESSOR FEATURE SETS 有权
公开(公告)号：US20130219154A1
公开(公告)日：2013-08-22
申请号：US13837923
申请日：2013-03-15
申请人： Don A. Van Dyke , Michael Mishaeli , Ittai Anati , Baiju V. Patel , Will Deutsch , Rajesh Shah , Gilbert Neiger , James B. Crossland , Chris J. Newburn , Bryant E. Bigbee , Muhammad Faisal Azeem , John L. Reid , Dion Rodgers
发明人： Don A. Van Dyke , Michael Mishaeli , Ittai Anati , Baiju V. Patel , Will Deutsch , Rajesh Shah , Gilbert Neiger , James B. Crossland , Chris J. Newburn , Bryant E. Bigbee , Muhammad Faisal Azeem , John L. Reid , Dion Rodgers
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30003 , G06F9/30101 , G06F9/461
摘要： Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.

6. 发明申请

US20120166767A1 SYSTEM, APPARATUS, AND METHOD FOR SEGMENT REGISTER READ AND WRITE REGARDLESS OF PRIVILEGE LEVEL 有权
标题翻译：系统，设备和分段注册读取和写入权限的优先权级别
公开(公告)号：US20120166767A1
公开(公告)日：2012-06-28
申请号：US12976981
申请日：2010-12-22
申请人： Baiju V. Patel , Gilbert Neiger , Martin G. Dixon , James S. Coke , James B. Crossland
发明人： Baiju V. Patel , Gilbert Neiger , Martin G. Dixon , James S. Coke , James B. Crossland
IPC分类号： G06F9/312
CPC分类号： G06F9/30032 , G06F9/30101 , G06F9/342
摘要： Embodiments of systems, apparatuses, and methods for performing privilege agnostic segment base register read or write instruction are described. An exemplary method may include fetching the privilege agnostic segment base register write instruction, wherein the privilege agnostic write instruction includes a 64-bit data source operand, decoding the fetched privilege agnostic segment base register write instruction, and executing the decoded privilege agnostic segment base register write instruction to write the 64-bit data of the source operand into the segment base register identified by the opcode of the privilege agnostic segment base register write instruction.
摘要翻译：描述用于执行特权不可知段段基址寄存器读或写指令的系统，装置和方法的实施例。一种示例性方法可以包括获取特权不可知段基址寄存器写指令，其中特权不可知写指令包括64位数据源操作数，对获取的特权不可知段基址寄存器写指令进行解码，以及执行解码的特权不可知段基址寄存器写指令将源操作数的64位数据写入由特权不可知段基址寄存器写指令的操作码标识的段基寄存器中。

7. 发明授权

US08010969B2 Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers 有权
标题翻译：在多个指令定序器上监视基于指令集的线程执行的机制
公开(公告)号：US08010969B2
公开(公告)日：2011-08-30
申请号：US11151809
申请日：2005-06-13
申请人： Richard A. Hankins , Gautham N. Chinya , Hong Wang , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Trung A. Diep , Xiang Zou , Baiju V. Patel , Paul M. Petersen , Sanjiv M. Shah , Ryan N. Rakvic , Prashant Sethi
发明人： Richard A. Hankins , Gautham N. Chinya , Hong Wang , Shivnandan D. Kaushik , Bryant E. Bigbee , John P. Shen , Trung A. Diep , Xiang Zou , Baiju V. Patel , Paul M. Petersen , Sanjiv M. Shah , Ryan N. Rakvic , Prashant Sethi
IPC分类号： G06F3/00 , G06F9/46 , G06F7/38
CPC分类号： G06F11/3466 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.
摘要翻译：监控软件线程性能和更新发布或使用线程以减少性能阻碍事件的软件的技术。本发明的至少一个实施例使用硬件和/或软件定时器或计数器来监视与执行用户级线程相关联的各种事件并将这些事件报告回用户级软件程序，其可以使用该信息来避免或至少减少与用户级线程相关联的性能抑制事件。

8. 发明申请

US20110078389A1 MANAGING AND IMPLEMENTING METADATA IN CENTRAL PROCESSING UNIT USING REGISTER EXTENSIONS 有权
标题翻译：使用注册扩展管理和实施中央处理单元中的元数据
公开(公告)号：US20110078389A1
公开(公告)日：2011-03-31
申请号：US12571269
申请日：2009-09-30
申请人： Baiju V. Patel , Rajeev Gopalakrishna , Andrew F. Glew , Robert J. Kushlis , Don Alan Van Dyke , Joseph Frank Cihula , Asit K. Mallick , James B. Crossland , Gilbert Neiger , Scott Dion Rodgers , Martin Guy Dixon , Mark Jay Charney , Jocob Gottlieb
发明人： Baiju V. Patel , Rajeev Gopalakrishna , Andrew F. Glew , Robert J. Kushlis , Don Alan Van Dyke , Joseph Frank Cihula , Asit K. Mallick , James B. Crossland , Gilbert Neiger , Scott Dion Rodgers , Martin Guy Dixon , Mark Jay Charney , Jocob Gottlieb
IPC分类号： G06F9/30 , G06F12/02 , G06F9/302
CPC分类号： G06F9/3013 , G06F9/30105 , G06F9/30112 , G06F9/32 , G06F9/342 , G06F9/35 , G06F12/1441
摘要： A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.
摘要翻译：一组处理器的默认寄存器被扩展到计算机系统的处理器上的元数据寄存器。存储有数据的默认寄存器，而与数据相关的元数据分别存储在元数据寄存器上。

9. 发明授权

US5533020A ATM cell scheduler 失效
标题翻译： ATM信元调度器
公开(公告)号：US5533020A
公开(公告)日：1996-07-02
申请号：US332160
申请日：1994-10-31
申请人： Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Baiju V. Patel , Kevin G. Plotz , Frank A. Schaffa , Marc H. Willebeek-LeMair
发明人： Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Baiju V. Patel , Kevin G. Plotz , Frank A. Schaffa , Marc H. Willebeek-LeMair
IPC分类号： G06F13/00 , H04L12/56 , H04L29/06 , H04L29/08 , H04Q3/00 , H04Q11/04
CPC分类号： H04L12/5602 , H04Q11/0478 , H04L2012/5635 , H04L2012/5651 , H04L2012/5672 , H04L2012/5679
摘要： A method and apparatus for scheduling the transmission of a number of data streams over a common communications link, where each of the data streams conforms to a corresponding set of flow control parameters. Each of the data streams to be transmitted on the communications link is stored in a corresponding queue. The status of each queue is maintained, and a target transmission time is calculated for each queue. Signals are then generated for each queue at a time at least after the target transmission time, and these signals are used to indicate to a corresponding queue that is can transmit a cell on the link. Upon reception of a corresponding signal, a queue then transmits at least one cell onto the communications link.
摘要翻译：一种用于通过公共通信链路调度多个数据流的传输的方法和装置，其中每个数据流符合对应的一组流量控制参数。要在通信链路上发送的每个数据流都存储在相应的队列中。维护每个队列的状态，并计算每个队列的目标传输时间。然后至少在目标传输时间之后，每个队列生成信号，并且这些信号用于指示可以在链路上传送单元的相应队列。在接收到对应信号时，队列随后将至少一个小区发送到通信链路上。

10. 发明授权

US5337311A Apparatus for connecting two fiber distributed data interface rings 失效
标题翻译：用于连接两个光纤分布式数据接口环的设备
公开(公告)号：US5337311A
公开(公告)日：1994-08-09
申请号：US997796
申请日：1992-12-29
申请人： Louis P. Herzberg , Baiju V. Patel , Antonio Ruiz , Frank A. Schaffa , Marc H. Willebeek-LeMair
发明人： Louis P. Herzberg , Baiju V. Patel , Antonio Ruiz , Frank A. Schaffa , Marc H. Willebeek-LeMair
IPC分类号： H04L12/46 , H04J3/02
CPC分类号： H04L12/4625 , H04L12/4637
摘要： In standard token-based LANs (e.g., FDDI, Token Ring) an equal share of the ring bandwidth is made available to each node. Certain nodes (e.g., bridges, routers, servers) require a larger representation (bandwidth) than other nodes. A surrogate (bridge/router) node is presented which achieves this in a standard compliant manner. The bridge/router may serve as a surrogate on each ring representing multiple stations from the other ring. The multiplicity of stations is adjusted either statically or dynamically to provide sufficient added bandwidth to the surrogate to reduce delay and packet loss characteristic of the conventional single station bridge or router. The increased bandwidth utilization and FDDI ring performance resulting from the implementation of this invention is transparent to the individual stations and the ring in a way that is advantageous to both single media and multimedia usages within defined network local and non-local areas.
摘要翻译：在基于标准令牌的LAN（例如，FDDI，令牌环）中，环带宽的相等份额使得每个节点可用。某些节点（例如，网桥，路由器，服务器）需要比其他节点更大的表示（带宽）。提出了一种以标准兼容方式实现的代理（桥/路由器）节点。桥/路由器可以在每个环上作为替代，代表来自另一个环的多个站。静态或动态地调整站的多样性以向代理提供足够的附加带宽，以减少常规单站桥或路由器的延迟和分组丢失特性。由于实施本发明所带来的增加的带宽利用率和FDDI环的性能对于各个站和环以对于在限定的网络本地和非本地区域内的单个媒体和多媒体使用有利的方式是透明的。

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