专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070174589A1 Processor having inactive state of operation and method thereof 有权
标题翻译：具有无效操作状态的处理器及其方法
公开(公告)号：US20070174589A1
公开(公告)日：2007-07-26
申请号：US11319805
申请日：2005-12-29
申请人： Gila Kamhi , Zelig Wayner , Amit Gradstein , Yoad Yagil , Thierry Pons , Ittai Anati , Ranan Fraer
发明人： Gila Kamhi , Zelig Wayner , Amit Gradstein , Yoad Yagil , Thierry Pons , Ittai Anati , Ranan Fraer
IPC分类号： G06F9/30
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： Embodiments of the present invention provide a processor having an inactive state of operation and methods thereof. The processor, according to some demonstrative embodiments of the invention, the processor may include a controller to determine an inactive state of operation is to be entered, and to cause a predetermined set of one or more execution units to execute a predetermined sequence of one or more micro-operations prior to entering the inactive state. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供一种具有非活动状态的处理器及其方法。根据本发明的一些演示实施例的处理器，处理器可以包括用于确定要进入的不活动状态的控制器，并且使一个或多个执行单元的预定集合执行预定的一个或多个进入非活动状态之前的更多微操作。描述和要求保护其他实施例。

2. 发明授权

US07536485B2 Processor having inactive state of operation and method thereof 有权
标题翻译：具有无效操作状态的处理器及其方法
公开(公告)号：US07536485B2
公开(公告)日：2009-05-19
申请号：US11319805
申请日：2005-12-29
申请人： Gila Kamhi , Zelig Wayner , Amit Gradstein , Yoad Yagil , Thierry Pons , Ittai Anati , Ranan Fraer
发明人： Gila Kamhi , Zelig Wayner , Amit Gradstein , Yoad Yagil , Thierry Pons , Ittai Anati , Ranan Fraer
IPC分类号： G06F13/10 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： Embodiments of the present invention provide a processor having an inactive state of operation and methods thereof. The processor, according to some demonstrative embodiments of the invention, the processor may include a controller to determine an inactive state of operation is to be entered, and to cause a predetermined set of one or more execution units to execute a predetermined sequence of one or more micro-operations prior to entering the inactive state. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供一种具有非活动状态的处理器及其方法。根据本发明的一些演示实施例的处理器，处理器可以包括用于确定要进入的不活动状态的控制器，并且使一个或多个执行单元的预定集合执行预定的一个或多个进入非活动状态之前的更多微操作。描述和要求保护其他实施例。

3. 发明授权

US09092226B2 Efficient parallel floating point exception handling in a processor 有权
标题翻译：处理器中的高效并行浮点异常处理
公开(公告)号：US09092226B2
公开(公告)日：2015-07-28
申请号：US13325559
申请日：2011-12-14
申请人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Amit Gradstein , Guy Bale , Thierry Pons
发明人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Amit Gradstein , Guy Bale , Thierry Pons
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/30014 , G06F9/30036
摘要： Methods and apparatus are provided for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one example a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one example a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.
摘要翻译：提供了用于处理执行单指令多数据（SIMD）指令的处理器中的浮点异常的方法和装置。在一个示例中，识别用于SIMD浮点运算的数字异常，并且启动SIMD微操作以生成用于SIMD浮点运算的打包结果的两个打包部分结果。启动SIMD非规范化微操作以组合两个打包的部分结果并且对组合的打包部分结果的一个或多个元素进行非规范化，以生成具有一个或多个异常元素的SIMD浮点运算的打包结果。标志被设置和存储与打包部分结果以识别异常元素。在一个示例中，当SIMD归一化微操作在使用乘法时在SIMD浮点运算之前产生归一化的伪内部浮点表示。

4. 发明申请

US20140188967A1 Leading Change Anticipator Logic 有权
标题翻译：领先的变革预期逻辑
公开(公告)号：US20140188967A1
公开(公告)日：2014-07-03
申请号：US13729421
申请日：2012-12-28
申请人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
发明人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
IPC分类号： G06F17/10
CPC分类号： G06F7/74 , G06F5/012 , G06F7/485
摘要： In one embodiment, a processor includes at least one floating point unit. The at least one floating point unit may include an adder, leading change anticipator (LCA) logic, and a shifter. The adder may be to add a first operand X and a second operand Y to obtain an output operand having a bit length n. The LCA logic may be to: for each bit position i from n−1 to 1, obtain a set of propagation values and a set of bit values based on the first operand X and the second operand Y; and generate a LCA mask based on the set of propagation values and the set of bit values. The shifter may be to normalize the output operand based on the LCA mask. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个浮点单元。所述至少一个浮点单元可以包括加法器，引导改变预测器（LCA）逻辑和移位器。加法器可以添加第一操作数X和第二操作数Y以获得具有位长度n的输出操作数。 LCA逻辑可以是：对于从n-1到1的每个比特位置i，基于第一操作数X和第二操作数Y获得一组传播值和一组比特值; 并且基于传播值集合和位值集合来生成LCA掩码。移位器可以是基于LCA掩码来规范化输出操作数。描述和要求保护其他实施例。

5. 发明申请

US20140379773A1 FUSED MULTIPLY ADD OPERATIONS USING BIT MASKS 有权
标题翻译：使用位掩码的多功能加密操作
公开(公告)号：US20140379773A1
公开(公告)日：2014-12-25
申请号：US13926175
申请日：2013-06-25
申请人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
发明人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
IPC分类号： G06F7/483 , G06F7/485 , G06F7/487
CPC分类号： G06F7/483 , G06F7/5443 , G06F7/764
摘要： Systems and methods of performing a fused multiply add (FMA) operations are provided. In one embodiment, the length of the adder used by the FMA operation is less than 3*N, where N is the number of bits in the mantissa term of a floating point number. A mask may be used to perform the addition portion of the FMA operation using the adder. A second mask may be used to denormalize the result of the addition portion of the FMA operation if an underflow occurs.
摘要翻译：提供了执行融合乘法（FMA）操作的系统和方法。在一个实施例中，由FMA操作使用的加法器的长度小于3 * N，其中N是浮点数的尾数项中的位数。可以使用掩码来使用加法器来执行FMA操作的相加部分。如果发生下溢，则可以使用第二掩模来对FMA操作的添加部分的结果进行非规范化。

6. 发明申请

US20090327665A1 Efficient parallel floating point exception handling in a processor 有权
标题翻译：处理器中的高效并行浮点异常处理
公开(公告)号：US20090327665A1
公开(公告)日：2009-12-31
申请号：US12217084
申请日：2008-06-30
申请人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Amit Gradstein , Guy Bale , Thierry Pons
发明人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Amit Gradstein , Guy Bale , Thierry Pons
IPC分类号： G06F9/302
CPC分类号： G06F9/3861 , G06F9/30014 , G06F9/30036
摘要： Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.
摘要翻译：公开了用于处理执行单指令多数据（SIMD）指令的处理器中的浮点异常的方法和装置。在一个实施例中，识别用于SIMD浮点运算的数字异常，并启动SIMD微操作以产生用于SIMD浮点运算的打包结果的两个打包部分结果。启动SIMD非规范化微操作以组合两个打包的部分结果并且对组合的打包部分结果的一个或多个元素进行非规范化，以生成具有一个或多个异常元素的SIMD浮点运算的打包结果。标志被设置和存储与打包部分结果以识别异常元素。在一个实施例中，当SIMD标准化微操作在使用乘法时在SIMD浮点运算之前产生归一化的伪内部浮点表示。

7. 发明授权

US09542154B2 Fused multiply add operations using bit masks 有权
标题翻译：融合乘法使用位掩码添加操作
公开(公告)号：US09542154B2
公开(公告)日：2017-01-10
申请号：US13926175
申请日：2013-06-25
申请人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
发明人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
IPC分类号： G06F7/483 , G06F7/544 , G06F7/76
CPC分类号： G06F7/483 , G06F7/5443 , G06F7/764
摘要： Systems and methods of performing a fused multiply add (FMA) operations are provided. In one embodiment, the length of the adder used by the FMA operation is less than 3*N, where N is the number of bits in the mantissa term of a floating point number. A mask may be used to perform the addition portion of the FMA operation using the adder. A second mask may be used to denormalize the result of the addition portion of the FMA operation if an underflow occurs.
摘要翻译：提供了执行融合乘法（FMA）操作的系统和方法。在一个实施例中，由FMA操作使用的加法器的长度小于3 * N，其中N是浮点数的尾数项中的位数。可以使用掩码来使用加法器来执行FMA操作的相加部分。如果发生下溢，则可以使用第二掩模来对FMA操作的添加部分的结果进行非规范化。

8. 发明授权

US08918446B2 Reducing power consumption in multi-precision floating point multipliers 有权
标题翻译：降低多精度浮点乘法器的功耗
公开(公告)号：US08918446B2
公开(公告)日：2014-12-23
申请号：US12967607
申请日：2010-12-14
申请人： Brent R. Boswell , Thierry Pons , Tom Aviram
发明人： Brent R. Boswell , Thierry Pons , Tom Aviram
IPC分类号： G06F1/00 , G06F7/44 , G06F7/52 , G06F1/32
CPC分类号： G06F1/3287 , G06F1/3203 , G06F7/4876 , G06F7/52 , G06F7/5318 , G06F7/5324 , G06F7/5338 , G06F9/30014 , G06F2207/382 , G06F2207/3884 , Y02D10/171
摘要： Methods and apparatus relating to reducing power consumption in multi-precision floating point multipliers are described. In an embodiment, certain portions of a multiplier are disabled in response to two or more multiplication operations with the same data size and data type occurring back-to-back. Other embodiments are also claimed and described.
摘要翻译：描述了在多精度浮点乘法器中降低功耗的方法和装置。在一个实施例中，乘法器的某些部分响应于具有相同数据大小和数据类型的背对背而发生的两个或多个乘法运算被禁用。还要求保护和描述其它实施例。

9. 发明申请

US20120084533A1 Efficient Parallel Floating Point Exception Handling In A Processor 审中-公开
标题翻译：处理器中有效的并行浮点异常处理
公开(公告)号：US20120084533A1
公开(公告)日：2012-04-05
申请号：US13325559
申请日：2011-12-14
申请人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Arnit Gradstein , Guy Bale , Thierry Pons
发明人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Arnit Gradstein , Guy Bale , Thierry Pons
IPC分类号： G06F9/30 , G06F9/38 , G06F9/302
CPC分类号： G06F9/3861 , G06F9/30014 , G06F9/30036
摘要： Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.
摘要翻译：公开了用于处理执行单指令多数据（SIMD）指令的处理器中的浮点异常的方法和装置。在一个实施例中，识别用于SIMD浮点运算的数字异常，并启动SIMD微操作以产生用于SIMD浮点运算的打包结果的两个打包部分结果。启动SIMD非规范化微操作以组合两个打包的部分结果并且对组合的打包部分结果的一个或多个元素进行非规范化，以生成具有一个或多个异常元素的SIMD浮点运算的打包结果。标志被设置和存储与打包部分结果以识别异常元素。在一个实施例中，当SIMD标准化微操作在使用乘法时在SIMD浮点运算之前产生归一化的伪内部浮点表示。

10. 发明申请

US20070005940A1 System, apparatus and method of executing a micro operation 审中-公开
标题翻译：执行微操作的系统，装置和方法
公开(公告)号：US20070005940A1
公开(公告)日：2007-01-04
申请号：US11170076
申请日：2005-06-30
申请人： Zeev Sperber , Guillermo Savransky , Sagi Lahav , Thierry Pons , Stephan Jourdan
发明人： Zeev Sperber , Guillermo Savransky , Sagi Lahav , Thierry Pons , Stephan Jourdan
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3017 , G06F9/3824 , G06F9/3832
摘要： Embodiments of the present invention provide an apparatus, system, and method of routing a source operand. Some demonstrative embodiments my include replacing a source operand of a micro operation to be executed by an execution unit with a value type representing a source value, e.g., if the source operand corresponds to the source value. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供了一种用于路由源操作数的装置，系统和方法。一些说明性实施例，我的包括用代表源值的值类型替换由执行单元执行的微操作的源操作数，例如，如果源操作数对应于源值。描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式