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1. 发明授权

US4833601A Cache resiliency in processing a variety of address faults 失效
标题翻译：缓存弹性处理各种地址故障
公开(公告)号：US4833601A
公开(公告)日：1989-05-23
申请号：US55577
申请日：1987-05-28
申请人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
发明人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
IPC分类号： G06F11/00 , G06F11/07 , G06F11/14 , G06F11/16 , G06F12/08 , G06F12/10
CPC分类号： G06F11/073 , G06F11/0724 , G06F11/0793 , G06F12/0815 , G06F11/0757 , G06F11/141
摘要： A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units and a first in first out (FIFO) device which connects to a system bus of a tightly coupled data processing system. The cache subsystem includes a number of programmable control circuits which are connected to receive signals representative of the type of operations performable by the cache subsystem. These signals are logically combined for generating an output signal indicating whether or not the contents of the directiory memory should be flushed when any one of a number of types of address or system faults has been detected in order to maintain cache coherency.

2. 发明授权

US5379378A Data processing system having a bus command generated by one subsystem on behalf of another subsystem 失效
标题翻译：数据处理系统具有由一个子系统代表另一子系统产生的总线命令
公开(公告)号：US5379378A
公开(公告)日：1995-01-03
申请号：US773752
申请日：1991-10-10
申请人： Arthur Peters , Richard C. Zelley , Elmer W. Carroll , George J. Barlow , Chester M. Nibby, Jr. , James W. Keeley
发明人： Arthur Peters , Richard C. Zelley , Elmer W. Carroll , George J. Barlow , Chester M. Nibby, Jr. , James W. Keeley
IPC分类号： G06F13/362 , G06F13/26 , G06F13/38 , G06F13/42 , G06F15/16
CPC分类号： G06F13/4243
摘要： A data processing system includes a system management unit, a number of central subsystems, a main memory and a number of peripheral subsystems all coupled in common to a system bus. Any subsystem may generate a command which includes a first field specifying a destination subsystem, a second field specifying the operation the destination subsystem is to perform. If a response is required, the subsystem generating the initial command may specify a third subsystem for receiving the response command.
摘要翻译：数据处理系统包括系统管理单元，多个中央子系统，主存储器和多个共同连接到系统总线的外围子系统。任何子系统可以生成包括指定目的地子系统的第一字段的命令，指定目的地子系统要执行的操作的第二字段。如果需要响应，则生成初始命令的子系统可以指定用于接收响应命令的第三子系统。

3. 发明授权

US4910666A Apparatus for loading and verifying a control store memory of a central subsystem 失效
标题翻译：用于加载和验证中央子系统的控制存储器的装置
公开(公告)号：US4910666A
公开(公告)日：1990-03-20
申请号：US943984
申请日：1986-12-18
申请人： Chester M. Nibby, Jr. , Richard C. Zelley , Kenneth E. Bruce , George J. Barlow , James W. Keeley
发明人： Chester M. Nibby, Jr. , Richard C. Zelley , Kenneth E. Bruce , George J. Barlow , James W. Keeley
IPC分类号： G06F9/445 , G06F9/22 , G06F9/24
CPC分类号： G06F9/24
摘要： A central subsystem of a data processing system includes a writable control store which is loaded with firmware to control the central subsystem operations. The central subsystem logic is responsive to a sequence of commands from a system management facility to load the control store and verify that the control store firmware is loaded correctly.

4. 发明授权

US4799222A Address transform method and apparatus for transferring addresses 失效
标题翻译：用于传送地址的地址变换方法和装置
公开(公告)号：US4799222A
公开(公告)日：1989-01-17
申请号：US001124
申请日：1987-01-07
申请人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
发明人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
IPC分类号： G06F11/10 , G06F12/08 , G06F12/10 , G06F12/16
CPC分类号： G06F11/10 , G06F12/0802
摘要： An address path which transfers addresses from a number of sources includes an incrementing circuit. The address includes a plurality of address bits and integrity bits. The address bits are applied to the incrementing circuit while the integrity bits are applied in parallel to a programmable logic device (PLD). While the address is being transferred or incremented as required, the PLD independently generates a number of transform bits defining a characteristic of the number of address bits predicted to change state. Thereafter, the transform bits are used to transform the address integrity bits for transfer with the incremented address. The incremented address, transform bits and integrity bits are logically combined for verifying that the address was transferred and/or incremented without error.
摘要翻译：从多个源传送地址的地址路径包括递增电路。地址包括多个地址位和完整性位。地址位应用于递增电路，而完整性位并行应用于可编程逻辑器件（PLD）。当地址正在根据需要被传送或递增时，PLD独立地产生多个变换位，定义预测为改变状态的地址位数的特性。此后，变换位用于变换用于递增地址的传送的地址完整性位。逻辑地组合递增地址，变换位和完整性位，以验证地址是否被传送和/或递增而没有错误。

5. 发明授权

US5491790A Power-on sequencing apparatus for initializing and testing a system processing unit 失效
标题翻译：用于初始化和测试系统处理单元的上电排序装置
公开(公告)号：US5491790A
公开(公告)日：1996-02-13
申请号：US231856
申请日：1994-04-22
申请人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr. , Keith L. Petry , Thomas S. Hirsch
发明人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr. , Keith L. Petry , Thomas S. Hirsch
IPC分类号： G06F1/00 , G06F9/06 , G06F9/445 , G06F11/22 , G06F11/267
CPC分类号： G06F11/2236 , G06F11/22 , G06F9/4403
摘要： A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus. Following loading of the peer processor operating system, the EEPROM control circuits, in response to commands from the system bus, enable the microprocessor to address the second region for executing boot routines for loading its operating system.
摘要翻译：除了其他单元之外，处理单元与对等处理器，主存储器共同地耦合到系统总线，并且包括紧密耦合到也可从这样的总线访问的本地存储器的微处理器。处理单元还包括可寻址的电可擦除可编程只读存储器（EEPROM）单元，其耦合到微处理器和系统总线。 EEPROM单元存储在第一和第二分离区域中，两者分别占据通常分配用于存储微处理器引导代码，车载诊断（OBD）例程和操作系统引导例程的相同地址空间。 EEPROM控制电路在上电时，使EEPROM单元处理第一个区域以执行OBD例程，以验证处理单元是否正常工作，包括正确向连接到系统总线的单元发出命令的能力。在加载对等处理器操作系统之后，响应于来自系统总线的命令，EEPROM控制电路使得微处理器能够寻址用于执行用于加载其操作系统的引导例程的第二区域。

6. 发明授权

US5341501A Processor bus access 失效
标题翻译：处理器总线访问
公开(公告)号：US5341501A
公开(公告)日：1994-08-23
申请号：US771582
申请日：1991-10-04
申请人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr.
发明人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr.
IPC分类号： G06F13/368 , G06F9/46
CPC分类号： G06F13/368
摘要： A high performance microprocessor bus state machine couples to a synchronous local bus in common with another state machine for accessing a local memory according to a preestablished bus protocol. Circuit means cosines the state of a predetermined protocol bus signal indicating the release of the local bus and transitions of the clock signal which are not used for synchronizing the operations of the state machines. The resulting signal applies required address and control signals in advance to the local bus enabling the non-microprocessor state machine to generate the required address strobe to local memory on the next clock which follows the release of the local bus by the microprocessor which eliminates a clock cycle whenever local bus control passes from the microprocessor bus state machine to another state machine.
摘要翻译：高性能微处理器总线状态机根据预先建立的总线协议与另一状态机共同连接到同步局部总线，用于访问本地存储器。电路意味着使指示本地总线的释放和不用于同步状态机的操作的时钟信号的转换的预定的协议总线信号的状态。所产生的信号预先将所需的地址和控制信号施加到本地总线，使得非微处理器状态机能够在微处理器释放本地总线之后的下一个时钟产生所需的地址选通脉冲，从而消除时钟当本地总线控制从微处理器总线状态机传递到另一状态机时，循环。

7. 发明授权

US4764862A Resilient bus system 失效
标题翻译：弹性总线系统
公开(公告)号：US4764862A
公开(公告)日：1988-08-16
申请号：US717201
申请日：1985-03-28
申请人： George J. Barlow , James W. Keeley
发明人： George J. Barlow , James W. Keeley
IPC分类号： G06F11/00 , G06F13/42 , G06F13/14
CPC分类号： G06F13/4213 , G06F11/00
摘要： A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and like checking apparatus for verifying that the different parts of a request received from such unit over the bus are valid based upon the states of accompanying function identification signals. When less than all of the parts of the request defined as requiring verification are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.
摘要翻译：数据处理系统包括多个单元，其被耦合以在分配的总线传送周期期间通过系统总线在单元之间传送包括数据，命令和完整性信号的请求。每个单元包括用于确认从其他单元接收的请求的响应装置。多个单元中的每一个还包括重试设备和类似的检查装置，用于根据伴随的功能识别信号的状态来验证从该单元接收的请求的不同部分是否有效。当被检测为需要验证的请求的全部部分被检测为有效时，接收单元不接受该请求并禁止其响应装置产生响应。这样可以防止系统完整性受到损害，并允许每个重试设备的单元在随后的总线传输周期内重试该请求。

8. 发明授权

US4724519A Channel number priority assignment apparatus 失效
标题翻译：频道编号优先分配装置
公开(公告)号：US4724519A
公开(公告)日：1988-02-09
申请号：US750117
申请日：1985-06-28
申请人： George J. Barlow , James W. Keeley , Elmer W. Carroll
发明人： George J. Barlow , James W. Keeley , Elmer W. Carroll
IPC分类号： G06F13/14 , G06F12/06 , G06F13/362 , G06F13/368 , G06F13/378 , G06F13/36
CPC分类号： G06F13/368 , G06F12/0623 , G06F13/378
摘要： A data processing system has a system bus network which includes a distributed priority network for transferring data asynchronously between a number of subsystems which couple to the bus. Each subsystem includes priority logic circuits coupled to receive a group of priority signals from the priority network which establish when the subsystem has the highest priority of the requesting subsystems to access the bus. The number of subsystems include a plurality of identical subsystems, each of which has a channel number assignment apparatus. The apparatus of each identical subsystem is connected to receive the same of at least one of the group of priority signals. During the idle state of the system bus, the apparatus of each identical subsystem operates to store a unique state of the priority signal which is defined as a function of the subsystem's position on the bus thereby automatically establishing a unique channel number value for each identical subsystem.
摘要翻译：数据处理系统具有系统总线网络，该系统总线网络包括用于在耦合到总线的多个子系统之间异步地传送数据的分布式优先级网络。每个子系统包括优先级逻辑电路，其被耦合以从优先级网络接收一组优先级信号，该优先级信号建立当子系统具有请求子系统访问总线的最高优先级时。子系统的数量包括多个相同的子系统，每个子系统具有信道号分配装置。每个相同子系统的装置被连接以接收该组优先级信号中的至少一个。在系统总线的空闲状态期间，每个相同子系统的装置操作以存储优先级信号的唯一状态，其被定义为总线上子系统位置的函数，从而为每个相同的子系统自动建立唯一的信道数值。

9. 发明授权

US5664200A Apparatus and method for providing more effective reiterations of interrupt requests in a multiprocessor system 失效
标题翻译：在多处理器系统中提供更有效重复中断请求的装置和方法
公开(公告)号：US5664200A
公开(公告)日：1997-09-02
申请号：US414983
申请日：1995-03-31
申请人： George J. Barlow , James W. Keeley
发明人： George J. Barlow , James W. Keeley
IPC分类号： G06F9/46 , G06F13/24 , G06F13/26 , G06F15/16 , G06F15/17 , G06F15/177 , G06F13/18
CPC分类号： G06F13/24 , G06F13/26 , G06F15/17
摘要： A multiprocessor computer system includes a number of processors, each processor having an interrupt mechanism and connecting in common to a system bus over which interrupt requests are communicated. When a processor accepts an interrupt request from another processor, it generates an acknowledge response on the system bus. If such processor contains a previous and pending interrupt request of an equal or higher priority level, it generates a not acknowledge response on the system bus and refuses the interrupt request. At the completion of servicing an interrupt request, each processor places on the system bus, an interrupt completed command including an address identifying such processor, a code designating a priority level to which it has switched and a code indicating that the processor has completing servicing an interrupt request. Each interrupt mechanism further includes interrupt retry means containing a refused interrupt register means for storing the channel address of the processor generating the not acknowledge in response and the priority level code contained in the interrupt request, and a level monitor logic unit connected to the system bus. The level monitor logic unit detects interrupt completed commands and compares the channel address and priority level code in the interrupt completed command to channel address and level code stored in the refused interrupt register means. When the processor channel addresses match and the level code is less than the level stored in the refused interrupt register means, the monitor logic unit generates a retry interrupt output. The processor retries the corresponding previously refused interrupt request upon receipt of the retry interrupt output.
摘要翻译：多处理器计算机系统包括多个处理器，每个处理器具有中断机制并且共同连接到通过其传送中断请求的系统总线。当处理器接受另一个处理器的中断请求时，它会在系统总线上产生一个确认响应。如果这样的处理器包含等于或更高优先级的先前和未决的中断请求，它将在系统总线上产生不确认响应并拒绝中断请求。在完成对中断请求的服务的完成时，每个处理器放置在系统总线上，一个中断完成命令，包括一个标识这样的处理器的地址，一个指定其所切换的优先级的代码，以及一个指示处理器完成服务的代码中断请求。每个中断机制还包括中断重试装置，其中包含一个拒绝中断寄存器装置，用于存储响应中产生不应答的处理器的通道地址以及中断请求中包含的优先级代码，以及连接到系统总线的电平监视逻辑单元。电平监视逻辑单元检测中断完成命令，并将中断完成命令中的通道地址和优先级代码与存储在拒绝中断寄存器装置中的通道地址和电平代码进行比较。当处理器通道地址匹配并且电平代码小于存储在拒绝中断寄存器装置中的电平时，监视器逻辑单元产生重试中断输出。接收到重试中断输出后，处理器重试相应的先前拒绝的中断请求。

10. 发明授权

US5446847A Programmable system bus priority network 失效
标题翻译：可编程系统总线优先网络
公开(公告)号：US5446847A
公开(公告)日：1995-08-29
申请号：US531
申请日：1993-01-04
申请人： James W. Keeley , George J. Barlow , Richard A. Lemay
发明人： James W. Keeley , George J. Barlow , Richard A. Lemay
IPC分类号： G06F13/372 , G06F13/18
CPC分类号： G06F13/372
摘要： A bus interface priority network provides access to a system bus by a plurality of different types of requestors as a function of the types of transactions they are required to process. The network includes programmable circuit for identifying the type of requestor and selecting a delay for accessing the system bus on the basis of requestor type thereby eliminating the need to adjust timing to the slowest requestor.
摘要翻译：总线接口优先级网络通过多个不同类型的请求者提供对系统总线的访问，作为它们需要处理的事务的类型的函数。该网络包括用于识别请求者的类型的可编程电路，并且基于请求者类型选择访问系统总线的延迟，从而消除了对最慢请求者调整定时的需要。

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