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1. 发明授权

US4833601A Cache resiliency in processing a variety of address faults 失效
标题翻译：缓存弹性处理各种地址故障
公开(公告)号：US4833601A
公开(公告)日：1989-05-23
申请号：US55577
申请日：1987-05-28
申请人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
发明人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
IPC分类号： G06F11/00 , G06F11/07 , G06F11/14 , G06F11/16 , G06F12/08 , G06F12/10
CPC分类号： G06F11/073 , G06F11/0724 , G06F11/0793 , G06F12/0815 , G06F11/0757 , G06F11/141
摘要： A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units and a first in first out (FIFO) device which connects to a system bus of a tightly coupled data processing system. The cache subsystem includes a number of programmable control circuits which are connected to receive signals representative of the type of operations performable by the cache subsystem. These signals are logically combined for generating an output signal indicating whether or not the contents of the directiory memory should be flushed when any one of a number of types of address or system faults has been detected in order to maintain cache coherency.

2. 发明授权

US5379378A Data processing system having a bus command generated by one subsystem on behalf of another subsystem 失效
标题翻译：数据处理系统具有由一个子系统代表另一子系统产生的总线命令
公开(公告)号：US5379378A
公开(公告)日：1995-01-03
申请号：US773752
申请日：1991-10-10
申请人： Arthur Peters , Richard C. Zelley , Elmer W. Carroll , George J. Barlow , Chester M. Nibby, Jr. , James W. Keeley
发明人： Arthur Peters , Richard C. Zelley , Elmer W. Carroll , George J. Barlow , Chester M. Nibby, Jr. , James W. Keeley
IPC分类号： G06F13/362 , G06F13/26 , G06F13/38 , G06F13/42 , G06F15/16
CPC分类号： G06F13/4243
摘要： A data processing system includes a system management unit, a number of central subsystems, a main memory and a number of peripheral subsystems all coupled in common to a system bus. Any subsystem may generate a command which includes a first field specifying a destination subsystem, a second field specifying the operation the destination subsystem is to perform. If a response is required, the subsystem generating the initial command may specify a third subsystem for receiving the response command.
摘要翻译：数据处理系统包括系统管理单元，多个中央子系统，主存储器和多个共同连接到系统总线的外围子系统。任何子系统可以生成包括指定目的地子系统的第一字段的命令，指定目的地子系统要执行的操作的第二字段。如果需要响应，则生成初始命令的子系统可以指定用于接收响应命令的第三子系统。

3. 发明授权

US4910666A Apparatus for loading and verifying a control store memory of a central subsystem 失效
标题翻译：用于加载和验证中央子系统的控制存储器的装置
公开(公告)号：US4910666A
公开(公告)日：1990-03-20
申请号：US943984
申请日：1986-12-18
申请人： Chester M. Nibby, Jr. , Richard C. Zelley , Kenneth E. Bruce , George J. Barlow , James W. Keeley
发明人： Chester M. Nibby, Jr. , Richard C. Zelley , Kenneth E. Bruce , George J. Barlow , James W. Keeley
IPC分类号： G06F9/445 , G06F9/22 , G06F9/24
CPC分类号： G06F9/24
摘要： A central subsystem of a data processing system includes a writable control store which is loaded with firmware to control the central subsystem operations. The central subsystem logic is responsive to a sequence of commands from a system management facility to load the control store and verify that the control store firmware is loaded correctly.

4. 发明授权

US4799222A Address transform method and apparatus for transferring addresses 失效
标题翻译：用于传送地址的地址变换方法和装置
公开(公告)号：US4799222A
公开(公告)日：1989-01-17
申请号：US001124
申请日：1987-01-07
申请人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
发明人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
IPC分类号： G06F11/10 , G06F12/08 , G06F12/10 , G06F12/16
CPC分类号： G06F11/10 , G06F12/0802
摘要： An address path which transfers addresses from a number of sources includes an incrementing circuit. The address includes a plurality of address bits and integrity bits. The address bits are applied to the incrementing circuit while the integrity bits are applied in parallel to a programmable logic device (PLD). While the address is being transferred or incremented as required, the PLD independently generates a number of transform bits defining a characteristic of the number of address bits predicted to change state. Thereafter, the transform bits are used to transform the address integrity bits for transfer with the incremented address. The incremented address, transform bits and integrity bits are logically combined for verifying that the address was transferred and/or incremented without error.
摘要翻译：从多个源传送地址的地址路径包括递增电路。地址包括多个地址位和完整性位。地址位应用于递增电路，而完整性位并行应用于可编程逻辑器件（PLD）。当地址正在根据需要被传送或递增时，PLD独立地产生多个变换位，定义预测为改变状态的地址位数的特性。此后，变换位用于变换用于递增地址的传送的地址完整性位。逻辑地组合递增地址，变换位和完整性位，以验证地址是否被传送和/或递增而没有错误。

5. 发明授权

US4077565A Error detection and correction locator circuits 失效
标题翻译：误差检测和校正定位电路
公开(公告)号：US4077565A
公开(公告)日：1978-03-07
申请号：US727820
申请日：1976-09-29
申请人： Chester M. Nibby, Jr. , George J. Barlow
发明人： Chester M. Nibby, Jr. , George J. Barlow
IPC分类号： G06F11/10 , H03M13/19 , G11C29/00 , G06F11/12
CPC分类号： G06F11/1048 , H03M13/19
摘要： A main memory system includes encoder and decoder circuits. The encoder circuits are connected to receive data bits and parity bits and from them generate check code bits which are stored with the data bits during a write cycle of operation. The decoder circuits are connected to receive data and check bits read out from memory during a read cycle of operation. The decoder circuits include a plurality of decoder circuits and error locator circuits. Circuits via exclusive OR circuits generate a number of syndrome bit signals. These signals are divided into first and second groups. The first group is coded to specify which one of a number of decoder circuits comprising the error locator circuits is to be enabled in the case of an error condition. The second group of signals is coded to designate the particular data bit to be corrected by the decoder circuits. Predetermined output terminals of each of the decoder circuits representative of valid single bit data error conditions are applied to a plurality of correction circuits for modification of the data signals as specified by the decoder circuits. Additionally, signals from predetermined output terminals of certain ones of the decoder circuits representative of certain single check code bit error conditions are utilized for providing the correct parity for the data signals associated therewith.
摘要翻译：主存储器系统包括编码器和解码器电路。编码器电路被连接以接收数据位和奇偶校验位，并且从它们产生在操作的写周期期间与数据位一起存储的校验码位。在操作的读取周期期间，解码器电路被连接以接收从存储器读出的数据和校验位。解码器电路包括多个解码器电路和误差定位器电路。通过异或电路的电路产生多个校正子位信号。这些信号被分成第一组和第二组。第一组被编码以指定在错误状况的情况下启用包括错误定位器电路的多个解码器电路中的哪一个。第二组信号被编码以指定由解码器电路校正的特定数据位。代表有效的单位数据错误条件的每个解码器电路的预定输出端子被施加到由解码器电路指定的用于修改数据信号的多个校正电路。此外，代表某些单个校验码位错误条件的某些解码器电路的来自预定输出端的信号被用于为与其相关联的数据信号提供正确的奇偶校验。

6. 发明授权

US4072853A Apparatus and method for storing parity encoded data from a plurality of input/output sources 失效
标题翻译：用于存储来自多个输入/输出源的奇偶校验编码数据的装置和方法
公开(公告)号：US4072853A
公开(公告)日：1978-02-07
申请号：US727821
申请日：1976-09-29
申请人： George J. Barlow , Chester M. Nibby, Jr.
发明人： George J. Barlow , Chester M. Nibby, Jr.
IPC分类号： G06F11/10 , G11C29/00 , G06F11/12
CPC分类号： G06F11/1024 , G06F11/1056
摘要： Apparatus and method are included in the main memory of the data processing system which receives data from a plurality of input/output devices connected to a common bus. During a write cycle of operation, a device applies a plurality of data byte signals together with associated parity bits for writing into an addressed storage location of memory. Error detection and correction encoder circuits are connected to receive the data bits and parity bits and from them generate check code bits which are coded to signal selectively the presence of an uncorrectable error condition in accordance with the parity bits from a given source. During a read cycle of operation, error detection and correction decoder circuits connected to the memory in response to the data and check code bits read out from an addressed location are operative to generate a number of syndrome bits having a predetermined characteristic for indicating the existence of an uncorrectable error condition when the parity bits associated with data signals when written originally into memory if checked would have indicated that the data was in error.
摘要翻译：数据处理系统的主存储器中包括装置和方法，该数据处理系统从连接到公共总线的多个输入/输出装置接收数据。在操作的写周期期间，设备将多个数据字节信号与相关联的奇偶校验位一起应用以写入存储器的寻址存储位置。连接错误检测和校正编码器电路以接收数据位和奇偶校验位，并且从它们产生编码的校验码位，以根据来自给定源的奇偶校验位选择性地存在不可校正的错误状况。在操作的读取周期期间，响应于从寻址位置读出的数据和校验码位连接到存储器的错误检测和校正解码器电路可操作以产生具有预定特性的多个校正子位，用于指示存在当与最初写入存储器的数据信号相关联的奇偶校验位如果被检查时，将会出现数据错误的情况，这是一个不可校正的错误状态。

7. 发明授权

US4558429A Pause apparatus for a memory controller with interleaved queuing apparatus 失效
标题翻译：暂停具有交错排队装置的存储器控制器的装置
公开(公告)号：US4558429A
公开(公告)日：1985-12-10
申请号：US331933
申请日：1981-12-17
申请人： George J. Barlow , Chester M. Nibby, Jr. , Robert B. Johnson
发明人： George J. Barlow , Chester M. Nibby, Jr. , Robert B. Johnson
IPC分类号： G06F13/16 , G06F12/00 , G06F13/18 , G06F13/28 , G06F13/32 , G06F9/00
CPC分类号： G06F13/18 , G06F13/28
摘要： A data processing system includes a plurality of memory command generating units which connect to a common bus network with a number of memory subsystems. Each subsystem includes a controller which controls the operation of a number of memory module units and includes a number of queue circuits for storing memory requests to be processed. The memory controller further includes control apparatus connected to monitor bus activity. In response to certain bus activity conditions occurring during multiword transfer operations, the control apparatus operates to lengthen the time between successive multiword transfers of data to the bus so as to ensure that new requestors having lower priorities than a memory controller gain access to an available queue notwithstanding the amount of bus delay incurred in transmitting their memory requests.
摘要翻译：数据处理系统包括多个存储器命令生成单元，其连接到具有多个存储器子系统的公共总线网络。每个子系统包括控制多个存储器模块单元的操作的控制器，并且包括用于存储要处理的存储器请求的多个队列电路。存储器控制器还包括连接到监视总线活动的控制装置。响应于在多字传输操作期间发生的某些总线活动条件，控制装置操作以将数据的连续多字传输之间的时间延长到总线，以便确保具有比存储器控制器低的优先级的新请求者获得对可用队列的访问尽管在发送其内存请求时发生总线延迟的数量。

8. 发明授权

US5367697A Means for providing a graceful power shut-down capability in a multiprocessor system having certain processors not inherently having a power shut-down capability 失效
标题翻译：用于在具有某些处理器的多处理器系统中提供优雅的电源关闭能力的手段，该处理器本身不具有电源关闭能力
公开(公告)号：US5367697A
公开(公告)日：1994-11-22
申请号：US781513
申请日：1991-10-22
申请人： George J. Barlow , James W. Keeley
发明人： George J. Barlow , James W. Keeley
IPC分类号： G06F11/00 , G06F1/30
CPC分类号： G06F11/1441
摘要： A multiprocessor computer system includes first processors, second processors, a system management means for performing system management functions, including detecting pending power shut-downs and sending power shut-down messages addressed to each of the first processors warning of pending power shut-downs, and a system bus for communication between the first and second processors and the system management means, including the communication of pending power shut-down messages. The first processors include interrupt handling means responsive to pending power shut-down messages for executing power shut-down routines for placing the first processors into a known state before power termination, but the second processors inherently do not include a power shut-down capability. In each of the second processors, a power shut-down means is provided to place the second processors in a known state before a power termination, including a bus monitor connected from the system bus and responsive to any power shut-down message addressed to a first processor for generating an output indicating the occurrence of a power shut-down message to a first processor. The second processor also includes non-maskable interrupt logic connected from the power shut-down message output of the bus monitor and responsive to the power shut-down message output of the bus monitor for generating a non-maskable interrupt output to the second processor. The second processor is in turn responsive to a non-maskable interrupt output of the non-maskable logic for querying the non-maskable logic to determine the nature of the interrupt, and responsive to the indicated occurrence of a power shut-down message to any first processor for executing a power shut-down routine for placing the second processor in a known state before the termination of power.
摘要翻译：多处理器计算机系统包括第一处理器，第二处理器，用于执行系统管理功能的系统管理装置，包括检测待处理的电源关闭，以及发送寻址到每个第一处理器的停电功率停止消息，以及用于在第一和第二处理器与系统管理装置之间进行通信的系统总线，包括待处理的电力关闭消息的通信。第一处理器包括响应于等待的电源关闭消息的中断处理装置，用于执行电源关闭例程，以在电源终止之前将第一处理器置于已知状态，但是第二处理器固有地不包括电源关闭功能。在每个第二处理器中，提供电源关闭装置以在电源终止之前将第二处理器置于已知状态，包括从系统总线连接的总线监视器，并且响应于任何电源关闭消息第一处理器，用于产生指示向第一处理器发出电力关闭消息的输出。第二处理器还包括从总线监视器的电源关闭消息输出连接的不可屏蔽中断逻辑，并且响应于总线监视器的电源关闭消息输出，以产生对第二处理器的不可屏蔽中断输出。第二处理器又响应于不可屏蔽逻辑的不可屏蔽中断输出，用于查询不可屏蔽逻辑以确定中断的性质，并且响应于所指示的电力关闭消息发生到任何第一处理器，用于在电源结束之前执行用于将第二处理器置于已知状态的电源关闭程序。

9. 发明授权

US4763243A Resilient bus system 失效
标题翻译：弹性总线系统
公开(公告)号：US4763243A
公开(公告)日：1988-08-09
申请号：US623264
申请日：1984-06-21
申请人： George J. Barlow , James W. Keeley
发明人： George J. Barlow , James W. Keeley
IPC分类号： G06F11/00 , G06F13/42 , G06F13/14 , G06F13/38
CPC分类号： G06F13/4213 , G06F11/00
摘要： A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and checking apparatus for verifying that all of the parts of a request received from such unit over the bus are valid. When less than all of the parts of the request are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.
摘要翻译：数据处理系统包括多个单元，其被耦合以在分配的总线传送周期期间通过系统总线在单元之间传送包括数据，命令和完整性信号的请求。每个单元包括用于确认从其他单元接收的请求的响应装置。多个单元中的每一个还包括重试设备和检查装置，用于验证从总线上接收到的单元的所有请求的所有部分都是有效的。当小于所有请求的部分被检测为有效时，接收单元不接受该请求并且禁止其响应装置产生响应。这样可以防止系统完整性受到损害，并允许每个重试设备的单元在随后的总线传输周期内重试该请求。

10. 发明授权

US4764862A Resilient bus system 失效
标题翻译：弹性总线系统
公开(公告)号：US4764862A
公开(公告)日：1988-08-16
申请号：US717201
申请日：1985-03-28
申请人： George J. Barlow , James W. Keeley
发明人： George J. Barlow , James W. Keeley
IPC分类号： G06F11/00 , G06F13/42 , G06F13/14
CPC分类号： G06F13/4213 , G06F11/00
摘要： A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and like checking apparatus for verifying that the different parts of a request received from such unit over the bus are valid based upon the states of accompanying function identification signals. When less than all of the parts of the request defined as requiring verification are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.
摘要翻译：数据处理系统包括多个单元，其被耦合以在分配的总线传送周期期间通过系统总线在单元之间传送包括数据，命令和完整性信号的请求。每个单元包括用于确认从其他单元接收的请求的响应装置。多个单元中的每一个还包括重试设备和类似的检查装置，用于根据伴随的功能识别信号的状态来验证从该单元接收的请求的不同部分是否有效。当被检测为需要验证的请求的全部部分被检测为有效时，接收单元不接受该请求并禁止其响应装置产生响应。这样可以防止系统完整性受到损害，并允许每个重试设备的单元在随后的总线传输周期内重试该请求。

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