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1. 发明授权

US5491790A Power-on sequencing apparatus for initializing and testing a system processing unit 失效
标题翻译：用于初始化和测试系统处理单元的上电排序装置
公开(公告)号：US5491790A
公开(公告)日：1996-02-13
申请号：US231856
申请日：1994-04-22
申请人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr. , Keith L. Petry , Thomas S. Hirsch
发明人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr. , Keith L. Petry , Thomas S. Hirsch
IPC分类号： G06F1/00 , G06F9/06 , G06F9/445 , G06F11/22 , G06F11/267
CPC分类号： G06F11/2236 , G06F11/22 , G06F9/4403
摘要： A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus. Following loading of the peer processor operating system, the EEPROM control circuits, in response to commands from the system bus, enable the microprocessor to address the second region for executing boot routines for loading its operating system.
摘要翻译：除了其他单元之外，处理单元与对等处理器，主存储器共同地耦合到系统总线，并且包括紧密耦合到也可从这样的总线访问的本地存储器的微处理器。处理单元还包括可寻址的电可擦除可编程只读存储器（EEPROM）单元，其耦合到微处理器和系统总线。 EEPROM单元存储在第一和第二分离区域中，两者分别占据通常分配用于存储微处理器引导代码，车载诊断（OBD）例程和操作系统引导例程的相同地址空间。 EEPROM控制电路在上电时，使EEPROM单元处理第一个区域以执行OBD例程，以验证处理单元是否正常工作，包括正确向连接到系统总线的单元发出命令的能力。在加载对等处理器操作系统之后，响应于来自系统总线的命令，EEPROM控制电路使得微处理器能够寻址用于执行用于加载其操作系统的引导例程的第二区域。

2. 发明授权

US5341501A Processor bus access 失效
标题翻译：处理器总线访问
公开(公告)号：US5341501A
公开(公告)日：1994-08-23
申请号：US771582
申请日：1991-10-04
申请人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr.
发明人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr.
IPC分类号： G06F13/368 , G06F9/46
CPC分类号： G06F13/368
摘要： A high performance microprocessor bus state machine couples to a synchronous local bus in common with another state machine for accessing a local memory according to a preestablished bus protocol. Circuit means cosines the state of a predetermined protocol bus signal indicating the release of the local bus and transitions of the clock signal which are not used for synchronizing the operations of the state machines. The resulting signal applies required address and control signals in advance to the local bus enabling the non-microprocessor state machine to generate the required address strobe to local memory on the next clock which follows the release of the local bus by the microprocessor which eliminates a clock cycle whenever local bus control passes from the microprocessor bus state machine to another state machine.
摘要翻译：高性能微处理器总线状态机根据预先建立的总线协议与另一状态机共同连接到同步局部总线，用于访问本地存储器。电路意味着使指示本地总线的释放和不用于同步状态机的操作的时钟信号的转换的预定的协议总线信号的状态。所产生的信号预先将所需的地址和控制信号施加到本地总线，使得非微处理器状态机能够在微处理器释放本地总线之后的下一个时钟产生所需的地址选通脉冲，从而消除时钟当本地总线控制从微处理器总线状态机传递到另一状态机时，循环。

3. 发明授权

US4833601A Cache resiliency in processing a variety of address faults 失效
标题翻译：缓存弹性处理各种地址故障
公开(公告)号：US4833601A
公开(公告)日：1989-05-23
申请号：US55577
申请日：1987-05-28
申请人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
发明人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
IPC分类号： G06F11/00 , G06F11/07 , G06F11/14 , G06F11/16 , G06F12/08 , G06F12/10
CPC分类号： G06F11/073 , G06F11/0724 , G06F11/0793 , G06F12/0815 , G06F11/0757 , G06F11/141
摘要： A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units and a first in first out (FIFO) device which connects to a system bus of a tightly coupled data processing system. The cache subsystem includes a number of programmable control circuits which are connected to receive signals representative of the type of operations performable by the cache subsystem. These signals are logically combined for generating an output signal indicating whether or not the contents of the directiory memory should be flushed when any one of a number of types of address or system faults has been detected in order to maintain cache coherency.

4. 发明授权

US5379378A Data processing system having a bus command generated by one subsystem on behalf of another subsystem 失效
标题翻译：数据处理系统具有由一个子系统代表另一子系统产生的总线命令
公开(公告)号：US5379378A
公开(公告)日：1995-01-03
申请号：US773752
申请日：1991-10-10
申请人： Arthur Peters , Richard C. Zelley , Elmer W. Carroll , George J. Barlow , Chester M. Nibby, Jr. , James W. Keeley
发明人： Arthur Peters , Richard C. Zelley , Elmer W. Carroll , George J. Barlow , Chester M. Nibby, Jr. , James W. Keeley
IPC分类号： G06F13/362 , G06F13/26 , G06F13/38 , G06F13/42 , G06F15/16
CPC分类号： G06F13/4243
摘要： A data processing system includes a system management unit, a number of central subsystems, a main memory and a number of peripheral subsystems all coupled in common to a system bus. Any subsystem may generate a command which includes a first field specifying a destination subsystem, a second field specifying the operation the destination subsystem is to perform. If a response is required, the subsystem generating the initial command may specify a third subsystem for receiving the response command.
摘要翻译：数据处理系统包括系统管理单元，多个中央子系统，主存储器和多个共同连接到系统总线的外围子系统。任何子系统可以生成包括指定目的地子系统的第一字段的命令，指定目的地子系统要执行的操作的第二字段。如果需要响应，则生成初始命令的子系统可以指定用于接收响应命令的第三子系统。

5. 发明授权

US4910666A Apparatus for loading and verifying a control store memory of a central subsystem 失效
标题翻译：用于加载和验证中央子系统的控制存储器的装置
公开(公告)号：US4910666A
公开(公告)日：1990-03-20
申请号：US943984
申请日：1986-12-18
申请人： Chester M. Nibby, Jr. , Richard C. Zelley , Kenneth E. Bruce , George J. Barlow , James W. Keeley
发明人： Chester M. Nibby, Jr. , Richard C. Zelley , Kenneth E. Bruce , George J. Barlow , James W. Keeley
IPC分类号： G06F9/445 , G06F9/22 , G06F9/24
CPC分类号： G06F9/24
摘要： A central subsystem of a data processing system includes a writable control store which is loaded with firmware to control the central subsystem operations. The central subsystem logic is responsive to a sequence of commands from a system management facility to load the control store and verify that the control store firmware is loaded correctly.

6. 发明授权

US4799222A Address transform method and apparatus for transferring addresses 失效
标题翻译：用于传送地址的地址变换方法和装置
公开(公告)号：US4799222A
公开(公告)日：1989-01-17
申请号：US001124
申请日：1987-01-07
申请人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
发明人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
IPC分类号： G06F11/10 , G06F12/08 , G06F12/10 , G06F12/16
CPC分类号： G06F11/10 , G06F12/0802
摘要： An address path which transfers addresses from a number of sources includes an incrementing circuit. The address includes a plurality of address bits and integrity bits. The address bits are applied to the incrementing circuit while the integrity bits are applied in parallel to a programmable logic device (PLD). While the address is being transferred or incremented as required, the PLD independently generates a number of transform bits defining a characteristic of the number of address bits predicted to change state. Thereafter, the transform bits are used to transform the address integrity bits for transfer with the incremented address. The incremented address, transform bits and integrity bits are logically combined for verifying that the address was transferred and/or incremented without error.
摘要翻译：从多个源传送地址的地址路径包括递增电路。地址包括多个地址位和完整性位。地址位应用于递增电路，而完整性位并行应用于可编程逻辑器件（PLD）。当地址正在根据需要被传送或递增时，PLD独立地产生多个变换位，定义预测为改变状态的地址位数的特性。此后，变换位用于变换用于递增地址的传送的地址完整性位。逻辑地组合递增地址，变换位和完整性位，以验证地址是否被传送和/或递增而没有错误。

7. 发明授权

US5446847A Programmable system bus priority network 失效
标题翻译：可编程系统总线优先网络
公开(公告)号：US5446847A
公开(公告)日：1995-08-29
申请号：US531
申请日：1993-01-04
申请人： James W. Keeley , George J. Barlow , Richard A. Lemay
发明人： James W. Keeley , George J. Barlow , Richard A. Lemay
IPC分类号： G06F13/372 , G06F13/18
CPC分类号： G06F13/372
摘要： A bus interface priority network provides access to a system bus by a plurality of different types of requestors as a function of the types of transactions they are required to process. The network includes programmable circuit for identifying the type of requestor and selecting a delay for accessing the system bus on the basis of requestor type thereby eliminating the need to adjust timing to the slowest requestor.
摘要翻译：总线接口优先级网络通过多个不同类型的请求者提供对系统总线的访问，作为它们需要处理的事务的类型的函数。该网络包括用于识别请求者的类型的可编程电路，并且基于请求者类型选择访问系统总线的延迟，从而消除了对最慢请求者调整定时的需要。

8. 发明授权

US5341495A Bus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocols 失效
标题翻译：总线控制器具有用于转换命令和控制从具有不同总线协议的系统总线到同步总线的访问的状态机
公开(公告)号：US5341495A
公开(公告)日：1994-08-23
申请号：US771297
申请日：1991-10-04
申请人： Thomas F. Joyce , James W. Keeley , Richard A. Lemay , Bruno DiPlacido, Jr. , Martin M. Massucci
发明人： Thomas F. Joyce , James W. Keeley , Richard A. Lemay , Bruno DiPlacido, Jr. , Martin M. Massucci
IPC分类号： G06F13/40 , G06F13/42 , G06F13/00 , G06F13/38
CPC分类号： G06F13/4027
摘要： A processing unit tightly couples to a system bus which utilizes a split cycle bus protocol and includes a local memory which is accessible from such bus. The local memory couples to a high speed synchronous bus which operates according to a predetermined bus protocol. The processing unit includes a state machine which couples to the high speed synchronous bus and to the asynchronous system bus. The state machine emulates the predetermined bus synchronous protocol in transferring commands issued to the local memory from the system bus which uses the split cycle protocol.
摘要翻译：处理单元紧密地耦合到利用分离循环总线协议的系统总线，并且包括可以从这种总线访问的本地存储器。本地存储器耦合到根据预定总线协议操作的高速同步总线。处理单元包括耦合到高速同步总线和异步系统总线的状态机。状态机在从使用分离周期协议的系统总线传送发给本地存储器的命令时模拟预定的总线同步协议。

9. 发明授权

US5293384A Microprocessor bus interface protocol analyzer 失效
标题翻译：微处理器总线接口协议分析仪
公开(公告)号：US5293384A
公开(公告)日：1994-03-08
申请号：US771581
申请日：1991-10-04
申请人： James W. Keeley , Richard A. Lemay
发明人： James W. Keeley , Richard A. Lemay
IPC分类号： G06F13/42 , G06F11/00
CPC分类号： G06F13/4217
摘要： A high performance microprocessor has associated therewith, protocol monitoring apparatus for monitoring all of the commands issued by the microprocessor and detecting when the protocol was not completed properly or completed within certain preestablished periods of time. When the monitor/timing circuits detect a protocol error, the monitoring apparatus operates to generate an output control signal which unwedges the microprocessor enabling it to continue further processing. Additionally, the monitoring apparatus includes a register for storing the address and command that the microprocessor was executing at the time of the protocol error. The same register is also used to capture address and command information for any other type of error.
摘要翻译：高性能微处理器与其相关联，用于监视由微处理器发出的所有命令的协议监视装置，以及检测协议何时未正确完成或在某些预先建立的时间段内完成。当监视器/定时电路检测到协议错误时，监视装置操作以产生输出控制信号，该输出控制信号使微处理器能够继续进行进一步的处理。此外，监视装置包括用于存储微处理器在协议错误时执行的地址和命令的寄存器。相同的寄存器也用于捕获任何其他类型错误的地址和命令信息。

10. 发明授权

US5193181A Recovery method and apparatus for a pipelined processing unit of a multiprocessor system 失效
标题翻译：多处理器系统管道处理单元的恢复方法和装置
公开(公告)号：US5193181A
公开(公告)日：1993-03-09
申请号：US593458
申请日：1990-10-05
申请人： George J. Barlow , James W. Keeley , Richard A. Lemay , Jian-Kuo Shen , Robert V. Ledoux, deceased , Thomas F. Joyce , Richard P. Kelly , Robert C. Miller
发明人： George J. Barlow , James W. Keeley , Richard A. Lemay , Jian-Kuo Shen , Robert V. Ledoux, deceased , Thomas F. Joyce , Richard P. Kelly , Robert C. Miller
IPC分类号： G06F11/00 , G06F11/22
CPC分类号： G06F11/0793 , G06F11/0724 , G06F11/0766 , G06F11/004 , G06F11/2205
摘要： The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode. Control circuits execute a UEV handler microcode routine which reads the contents of syndrome registers included on each board containing the UEV indicator states in addition to error signals into register file working locations. The UEV signal is then cleared enabling the BIU to resume communications with the sytem bus.

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