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1. 发明授权

US4724519A Channel number priority assignment apparatus 失效
标题翻译：频道编号优先分配装置
公开(公告)号：US4724519A
公开(公告)日：1988-02-09
申请号：US750117
申请日：1985-06-28
申请人： George J. Barlow , James W. Keeley , Elmer W. Carroll
发明人： George J. Barlow , James W. Keeley , Elmer W. Carroll
IPC分类号： G06F13/14 , G06F12/06 , G06F13/362 , G06F13/368 , G06F13/378 , G06F13/36
CPC分类号： G06F13/368 , G06F12/0623 , G06F13/378
摘要： A data processing system has a system bus network which includes a distributed priority network for transferring data asynchronously between a number of subsystems which couple to the bus. Each subsystem includes priority logic circuits coupled to receive a group of priority signals from the priority network which establish when the subsystem has the highest priority of the requesting subsystems to access the bus. The number of subsystems include a plurality of identical subsystems, each of which has a channel number assignment apparatus. The apparatus of each identical subsystem is connected to receive the same of at least one of the group of priority signals. During the idle state of the system bus, the apparatus of each identical subsystem operates to store a unique state of the priority signal which is defined as a function of the subsystem's position on the bus thereby automatically establishing a unique channel number value for each identical subsystem.
摘要翻译：数据处理系统具有系统总线网络，该系统总线网络包括用于在耦合到总线的多个子系统之间异步地传送数据的分布式优先级网络。每个子系统包括优先级逻辑电路，其被耦合以从优先级网络接收一组优先级信号，该优先级信号建立当子系统具有请求子系统访问总线的最高优先级时。子系统的数量包括多个相同的子系统，每个子系统具有信道号分配装置。每个相同子系统的装置被连接以接收该组优先级信号中的至少一个。在系统总线的空闲状态期间，每个相同子系统的装置操作以存储优先级信号的唯一状态，其被定义为总线上子系统位置的函数，从而为每个相同的子系统自动建立唯一的信道数值。

2. 发明授权

US5274797A Multiprocessor system with centralized initialization, testing and monitoring of the system and providing centralized timing 失效
标题翻译：多处理器系统集中初始化，测试和监控系统并提供集中的时序
公开(公告)号：US5274797A
公开(公告)日：1993-12-28
申请号：US377785
申请日：1989-07-06
申请人： George J. Barlow , Elmer W. Carroll , James W. Keeley , Wallace A. Martland , Victor M. Morganti , Arthur Peters , Richard C. Zelley
发明人： George J. Barlow , Elmer W. Carroll , James W. Keeley , Wallace A. Martland , Victor M. Morganti , Arthur Peters , Richard C. Zelley
IPC分类号： G01P1/00 , G01P15/08 , G01P15/097 , G01P15/10 , G06F11/00 , G06F11/22 , G06F11/273 , G06F11/30 , G06F11/32 , G06F11/36 , G06F15/16
CPC分类号： G01P15/097 , G01P1/003 , G01P15/0802 , G06F11/22 , G06F11/328 , G01P2015/0828 , G06F11/0757 , G06F11/2294 , G06F11/32 , G06F11/321
摘要： A data processing unit includes a number of tightly coupled central subsystems, a number of peripheral subsystems, a main memory and a system management facility all coupled in common to a system bus. The system management unit has top priority on the system bus and includes centralized resources which provide apparatus for indicating the status of power and temperature, booting the subsystems, testing the subsystems, timing central subsystem functions, and allowing local and remote maintenance access to the subsystems. The system management facility receives commands from the central subystem to read from and write into the timers as well as to read the status of the overall system. The system management facility generates special commands to the central subsystem to indicate when the timers have decremented to ZERO as well as special commands to aid in hardware and software debugging.
摘要翻译：数据处理单元包括多个紧密耦合的中央子系统，多个外围子系统，主存储器和系统管理设备，其全部共同连接到系统总线。系统管理单元在系统总线上具有最高优先级，并且包括提供用于指示功率和温度状态的设备，引导子系统，测试子系统，定时中心子系统功能以及允许本地和远程维护对子系统的访问的集中资源。系统管理设施接收来自中央子系统的命令，以读取和写入定时器以及读取整个系统的状态。系统管理设备向中央子系统生成特殊命令，以指示定时器什么时候减少到零，以及特殊命令来辅助硬件和软件调试。

3. 发明授权

US5379378A Data processing system having a bus command generated by one subsystem on behalf of another subsystem 失效
标题翻译：数据处理系统具有由一个子系统代表另一子系统产生的总线命令
公开(公告)号：US5379378A
公开(公告)日：1995-01-03
申请号：US773752
申请日：1991-10-10
申请人： Arthur Peters , Richard C. Zelley , Elmer W. Carroll , George J. Barlow , Chester M. Nibby, Jr. , James W. Keeley
发明人： Arthur Peters , Richard C. Zelley , Elmer W. Carroll , George J. Barlow , Chester M. Nibby, Jr. , James W. Keeley
IPC分类号： G06F13/362 , G06F13/26 , G06F13/38 , G06F13/42 , G06F15/16
CPC分类号： G06F13/4243
摘要： A data processing system includes a system management unit, a number of central subsystems, a main memory and a number of peripheral subsystems all coupled in common to a system bus. Any subsystem may generate a command which includes a first field specifying a destination subsystem, a second field specifying the operation the destination subsystem is to perform. If a response is required, the subsystem generating the initial command may specify a third subsystem for receiving the response command.
摘要翻译：数据处理系统包括系统管理单元，多个中央子系统，主存储器和多个共同连接到系统总线的外围子系统。任何子系统可以生成包括指定目的地子系统的第一字段的命令，指定目的地子系统要执行的操作的第二字段。如果需要响应，则生成初始命令的子系统可以指定用于接收响应命令的第三子系统。

4. 发明授权

US5367697A Means for providing a graceful power shut-down capability in a multiprocessor system having certain processors not inherently having a power shut-down capability 失效
标题翻译：用于在具有某些处理器的多处理器系统中提供优雅的电源关闭能力的手段，该处理器本身不具有电源关闭能力
公开(公告)号：US5367697A
公开(公告)日：1994-11-22
申请号：US781513
申请日：1991-10-22
申请人： George J. Barlow , James W. Keeley
发明人： George J. Barlow , James W. Keeley
IPC分类号： G06F11/00 , G06F1/30
CPC分类号： G06F11/1441
摘要： A multiprocessor computer system includes first processors, second processors, a system management means for performing system management functions, including detecting pending power shut-downs and sending power shut-down messages addressed to each of the first processors warning of pending power shut-downs, and a system bus for communication between the first and second processors and the system management means, including the communication of pending power shut-down messages. The first processors include interrupt handling means responsive to pending power shut-down messages for executing power shut-down routines for placing the first processors into a known state before power termination, but the second processors inherently do not include a power shut-down capability. In each of the second processors, a power shut-down means is provided to place the second processors in a known state before a power termination, including a bus monitor connected from the system bus and responsive to any power shut-down message addressed to a first processor for generating an output indicating the occurrence of a power shut-down message to a first processor. The second processor also includes non-maskable interrupt logic connected from the power shut-down message output of the bus monitor and responsive to the power shut-down message output of the bus monitor for generating a non-maskable interrupt output to the second processor. The second processor is in turn responsive to a non-maskable interrupt output of the non-maskable logic for querying the non-maskable logic to determine the nature of the interrupt, and responsive to the indicated occurrence of a power shut-down message to any first processor for executing a power shut-down routine for placing the second processor in a known state before the termination of power.
摘要翻译：多处理器计算机系统包括第一处理器，第二处理器，用于执行系统管理功能的系统管理装置，包括检测待处理的电源关闭，以及发送寻址到每个第一处理器的停电功率停止消息，以及用于在第一和第二处理器与系统管理装置之间进行通信的系统总线，包括待处理的电力关闭消息的通信。第一处理器包括响应于等待的电源关闭消息的中断处理装置，用于执行电源关闭例程，以在电源终止之前将第一处理器置于已知状态，但是第二处理器固有地不包括电源关闭功能。在每个第二处理器中，提供电源关闭装置以在电源终止之前将第二处理器置于已知状态，包括从系统总线连接的总线监视器，并且响应于任何电源关闭消息第一处理器，用于产生指示向第一处理器发出电力关闭消息的输出。第二处理器还包括从总线监视器的电源关闭消息输出连接的不可屏蔽中断逻辑，并且响应于总线监视器的电源关闭消息输出，以产生对第二处理器的不可屏蔽中断输出。第二处理器又响应于不可屏蔽逻辑的不可屏蔽中断输出，用于查询不可屏蔽逻辑以确定中断的性质，并且响应于所指示的电力关闭消息发生到任何第一处理器，用于在电源结束之前执行用于将第二处理器置于已知状态的电源关闭程序。

5. 发明授权

US4833601A Cache resiliency in processing a variety of address faults 失效
标题翻译：缓存弹性处理各种地址故障
公开(公告)号：US4833601A
公开(公告)日：1989-05-23
申请号：US55577
申请日：1987-05-28
申请人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
发明人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
IPC分类号： G06F11/00 , G06F11/07 , G06F11/14 , G06F11/16 , G06F12/08 , G06F12/10
CPC分类号： G06F11/073 , G06F11/0724 , G06F11/0793 , G06F12/0815 , G06F11/0757 , G06F11/141
摘要： A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units and a first in first out (FIFO) device which connects to a system bus of a tightly coupled data processing system. The cache subsystem includes a number of programmable control circuits which are connected to receive signals representative of the type of operations performable by the cache subsystem. These signals are logically combined for generating an output signal indicating whether or not the contents of the directiory memory should be flushed when any one of a number of types of address or system faults has been detected in order to maintain cache coherency.

6. 发明授权

US4763243A Resilient bus system 失效
标题翻译：弹性总线系统
公开(公告)号：US4763243A
公开(公告)日：1988-08-09
申请号：US623264
申请日：1984-06-21
申请人： George J. Barlow , James W. Keeley
发明人： George J. Barlow , James W. Keeley
IPC分类号： G06F11/00 , G06F13/42 , G06F13/14 , G06F13/38
CPC分类号： G06F13/4213 , G06F11/00
摘要： A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and checking apparatus for verifying that all of the parts of a request received from such unit over the bus are valid. When less than all of the parts of the request are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.
摘要翻译：数据处理系统包括多个单元，其被耦合以在分配的总线传送周期期间通过系统总线在单元之间传送包括数据，命令和完整性信号的请求。每个单元包括用于确认从其他单元接收的请求的响应装置。多个单元中的每一个还包括重试设备和检查装置，用于验证从总线上接收到的单元的所有请求的所有部分都是有效的。当小于所有请求的部分被检测为有效时，接收单元不接受该请求并且禁止其响应装置产生响应。这样可以防止系统完整性受到损害，并允许每个重试设备的单元在随后的总线传输周期内重试该请求。

7. 发明授权

US4764862A Resilient bus system 失效
标题翻译：弹性总线系统
公开(公告)号：US4764862A
公开(公告)日：1988-08-16
申请号：US717201
申请日：1985-03-28
申请人： George J. Barlow , James W. Keeley
发明人： George J. Barlow , James W. Keeley
IPC分类号： G06F11/00 , G06F13/42 , G06F13/14
CPC分类号： G06F13/4213 , G06F11/00
摘要： A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and like checking apparatus for verifying that the different parts of a request received from such unit over the bus are valid based upon the states of accompanying function identification signals. When less than all of the parts of the request defined as requiring verification are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.
摘要翻译：数据处理系统包括多个单元，其被耦合以在分配的总线传送周期期间通过系统总线在单元之间传送包括数据，命令和完整性信号的请求。每个单元包括用于确认从其他单元接收的请求的响应装置。多个单元中的每一个还包括重试设备和类似的检查装置，用于根据伴随的功能识别信号的状态来验证从该单元接收的请求的不同部分是否有效。当被检测为需要验证的请求的全部部分被检测为有效时，接收单元不接受该请求并禁止其响应装置产生响应。这样可以防止系统完整性受到损害，并允许每个重试设备的单元在随后的总线传输周期内重试该请求。

8. 发明授权

US4802087A Multiprocessor level change synchronization apparatus 失效
标题翻译：多处理器级更改同步装置
公开(公告)号：US4802087A
公开(公告)日：1989-01-31
申请号：US879858
申请日：1986-06-27
申请人： James W. Keeley , George J. Barlow
发明人： James W. Keeley , George J. Barlow
IPC分类号： G06F15/16 , G06F9/46 , G06F9/48 , G06F13/20 , G06F13/24 , G06F13/26 , G06F15/177 , G06F13/14
CPC分类号： G06F9/4812 , G06F13/26
摘要： An apparatus is included within the bus interface circuits of each processing unit of a multiprocessing system which connect in common with the other units of the system to an asynchronous system bus. The apparatus and interrupt signal couple to the processing unit's level register and interrupt circuits. In response to a command specifying a level change, the apparatus conditions these circuits to store level and interrupt signals applied to the system bus as part of such CPU command during a bus cycle of operation granted to the processing unit on a priority basis. This ensures the reliable switching between interrupt levels and the notification of such level changes to the other units of the system without interference from other processing units.
摘要翻译：在多处理系统的每个处理单元的总线接口电路中包括一个装置，其与系统的其它单元共同连接到异步系统总线。设备和中断信号耦合到处理单元的电平寄存器和中断电路。响应于指定电平变化的命令，该设备使这些电路在优先基础上授予处理单元的总线运行周期期间将施加到系统总线的电平和中断信号作为这种CPU命令的一部分。这确保了中断级别之间的可靠切换和对系统的其他单元的这种电平改变的通知，而不受其他处理单元的干扰。

9. 发明授权

US4768148A Read in process memory apparatus 失效
标题翻译：读进程存储器
公开(公告)号：US4768148A
公开(公告)日：1988-08-30
申请号：US879856
申请日：1986-06-27
申请人： James W. Keeley , George J. Barlow
发明人： James W. Keeley , George J. Barlow
IPC分类号： G06F12/08 , G06F13/00 , G11C7/00
CPC分类号： G06F12/084 , G06F12/0859
摘要： A cache memory subsystem couples to main memory through interface circuits via a system bus in common with a plurality of central processing subsystems which have similar interface circuits. The cache memory subsystem includes multilevel directory memory and buffer memory pipeline stages shareable by at least a pair of processing units. A read in process (RIP) memory associated with the buffer memory stage is set to a predetermined state in response to each read request which produces a miss condition to identify the buffer memory location of a specific level in the buffer memory which has been preallocated. The contents of the buffer memory stage are maintained coherent with main memory by updating its contents in response to write requests applied to the system bus by other subsystems. Upon detecting the receipt of data prior to the receipt of the requested data which would make the buffer memory contents incoherent, the cache switches the state of control means associated with the RIP memory. Upon receipt of the requested data, the directory memory is accessed, the RIP memory is reset and the latest data is forwarded to the requesting processing unit as a function of the state of the control means.
摘要翻译：缓存存储器子系统通过与具有类似接口电路的多个中央处理子系统相同的系统总线通过接口电路耦合到主存储器。高速缓冲存储器子系统包括可由至少一对处理单元共享的多级目录存储器和缓冲存储器流水线级。响应于每个读取请求而将与缓冲存储器级相关联的读入处理（RIP）存储器设置为预定状态，该读取请求产生未预定条件，以识别已预先分配的缓冲存储器中的特定级别的缓冲存储器位置。缓冲存储器级的内容通过响应于由其他子系统应用于系统总线的写请求来更新其内容而与主存储器保持一致。在接收到所请求的数据之后检测到数据的接收将使缓冲存储器内容不连贯，高速缓存切换与RIP存储器相关联的控制装置的状态。在接收到所请求的数据时，访问目录存储器，RIP存储器被重置，并且最新数据作为控制装置的状态的函数被转发到请求处理单元。

10. 发明授权

US5664200A Apparatus and method for providing more effective reiterations of interrupt requests in a multiprocessor system 失效
标题翻译：在多处理器系统中提供更有效重复中断请求的装置和方法
公开(公告)号：US5664200A
公开(公告)日：1997-09-02
申请号：US414983
申请日：1995-03-31
申请人： George J. Barlow , James W. Keeley
发明人： George J. Barlow , James W. Keeley
IPC分类号： G06F9/46 , G06F13/24 , G06F13/26 , G06F15/16 , G06F15/17 , G06F15/177 , G06F13/18
CPC分类号： G06F13/24 , G06F13/26 , G06F15/17
摘要： A multiprocessor computer system includes a number of processors, each processor having an interrupt mechanism and connecting in common to a system bus over which interrupt requests are communicated. When a processor accepts an interrupt request from another processor, it generates an acknowledge response on the system bus. If such processor contains a previous and pending interrupt request of an equal or higher priority level, it generates a not acknowledge response on the system bus and refuses the interrupt request. At the completion of servicing an interrupt request, each processor places on the system bus, an interrupt completed command including an address identifying such processor, a code designating a priority level to which it has switched and a code indicating that the processor has completing servicing an interrupt request. Each interrupt mechanism further includes interrupt retry means containing a refused interrupt register means for storing the channel address of the processor generating the not acknowledge in response and the priority level code contained in the interrupt request, and a level monitor logic unit connected to the system bus. The level monitor logic unit detects interrupt completed commands and compares the channel address and priority level code in the interrupt completed command to channel address and level code stored in the refused interrupt register means. When the processor channel addresses match and the level code is less than the level stored in the refused interrupt register means, the monitor logic unit generates a retry interrupt output. The processor retries the corresponding previously refused interrupt request upon receipt of the retry interrupt output.
摘要翻译：多处理器计算机系统包括多个处理器，每个处理器具有中断机制并且共同连接到通过其传送中断请求的系统总线。当处理器接受另一个处理器的中断请求时，它会在系统总线上产生一个确认响应。如果这样的处理器包含等于或更高优先级的先前和未决的中断请求，它将在系统总线上产生不确认响应并拒绝中断请求。在完成对中断请求的服务的完成时，每个处理器放置在系统总线上，一个中断完成命令，包括一个标识这样的处理器的地址，一个指定其所切换的优先级的代码，以及一个指示处理器完成服务的代码中断请求。每个中断机制还包括中断重试装置，其中包含一个拒绝中断寄存器装置，用于存储响应中产生不应答的处理器的通道地址以及中断请求中包含的优先级代码，以及连接到系统总线的电平监视逻辑单元。电平监视逻辑单元检测中断完成命令，并将中断完成命令中的通道地址和优先级代码与存储在拒绝中断寄存器装置中的通道地址和电平代码进行比较。当处理器通道地址匹配并且电平代码小于存储在拒绝中断寄存器装置中的电平时，监视器逻辑单元产生重试中断输出。接收到重试中断输出后，处理器重试相应的先前拒绝的中断请求。

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