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1. 发明授权

US4833601A Cache resiliency in processing a variety of address faults 失效
标题翻译：缓存弹性处理各种地址故障
公开(公告)号：US4833601A
公开(公告)日：1989-05-23
申请号：US55577
申请日：1987-05-28
申请人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
发明人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
IPC分类号： G06F11/00 , G06F11/07 , G06F11/14 , G06F11/16 , G06F12/08 , G06F12/10
CPC分类号： G06F11/073 , G06F11/0724 , G06F11/0793 , G06F12/0815 , G06F11/0757 , G06F11/141
摘要： A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units and a first in first out (FIFO) device which connects to a system bus of a tightly coupled data processing system. The cache subsystem includes a number of programmable control circuits which are connected to receive signals representative of the type of operations performable by the cache subsystem. These signals are logically combined for generating an output signal indicating whether or not the contents of the directiory memory should be flushed when any one of a number of types of address or system faults has been detected in order to maintain cache coherency.

2. 发明授权

US5379378A Data processing system having a bus command generated by one subsystem on behalf of another subsystem 失效
标题翻译：数据处理系统具有由一个子系统代表另一子系统产生的总线命令
公开(公告)号：US5379378A
公开(公告)日：1995-01-03
申请号：US773752
申请日：1991-10-10
申请人： Arthur Peters , Richard C. Zelley , Elmer W. Carroll , George J. Barlow , Chester M. Nibby, Jr. , James W. Keeley
发明人： Arthur Peters , Richard C. Zelley , Elmer W. Carroll , George J. Barlow , Chester M. Nibby, Jr. , James W. Keeley
IPC分类号： G06F13/362 , G06F13/26 , G06F13/38 , G06F13/42 , G06F15/16
CPC分类号： G06F13/4243
摘要： A data processing system includes a system management unit, a number of central subsystems, a main memory and a number of peripheral subsystems all coupled in common to a system bus. Any subsystem may generate a command which includes a first field specifying a destination subsystem, a second field specifying the operation the destination subsystem is to perform. If a response is required, the subsystem generating the initial command may specify a third subsystem for receiving the response command.
摘要翻译：数据处理系统包括系统管理单元，多个中央子系统，主存储器和多个共同连接到系统总线的外围子系统。任何子系统可以生成包括指定目的地子系统的第一字段的命令，指定目的地子系统要执行的操作的第二字段。如果需要响应，则生成初始命令的子系统可以指定用于接收响应命令的第三子系统。

3. 发明授权

US4910666A Apparatus for loading and verifying a control store memory of a central subsystem 失效
标题翻译：用于加载和验证中央子系统的控制存储器的装置
公开(公告)号：US4910666A
公开(公告)日：1990-03-20
申请号：US943984
申请日：1986-12-18
申请人： Chester M. Nibby, Jr. , Richard C. Zelley , Kenneth E. Bruce , George J. Barlow , James W. Keeley
发明人： Chester M. Nibby, Jr. , Richard C. Zelley , Kenneth E. Bruce , George J. Barlow , James W. Keeley
IPC分类号： G06F9/445 , G06F9/22 , G06F9/24
CPC分类号： G06F9/24
摘要： A central subsystem of a data processing system includes a writable control store which is loaded with firmware to control the central subsystem operations. The central subsystem logic is responsive to a sequence of commands from a system management facility to load the control store and verify that the control store firmware is loaded correctly.

4. 发明授权

US4799222A Address transform method and apparatus for transferring addresses 失效
标题翻译：用于传送地址的地址变换方法和装置
公开(公告)号：US4799222A
公开(公告)日：1989-01-17
申请号：US001124
申请日：1987-01-07
申请人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
发明人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
IPC分类号： G06F11/10 , G06F12/08 , G06F12/10 , G06F12/16
CPC分类号： G06F11/10 , G06F12/0802
摘要： An address path which transfers addresses from a number of sources includes an incrementing circuit. The address includes a plurality of address bits and integrity bits. The address bits are applied to the incrementing circuit while the integrity bits are applied in parallel to a programmable logic device (PLD). While the address is being transferred or incremented as required, the PLD independently generates a number of transform bits defining a characteristic of the number of address bits predicted to change state. Thereafter, the transform bits are used to transform the address integrity bits for transfer with the incremented address. The incremented address, transform bits and integrity bits are logically combined for verifying that the address was transferred and/or incremented without error.
摘要翻译：从多个源传送地址的地址路径包括递增电路。地址包括多个地址位和完整性位。地址位应用于递增电路，而完整性位并行应用于可编程逻辑器件（PLD）。当地址正在根据需要被传送或递增时，PLD独立地产生多个变换位，定义预测为改变状态的地址位数的特性。此后，变换位用于变换用于递增地址的传送的地址完整性位。逻辑地组合递增地址，变换位和完整性位，以验证地址是否被传送和/或递增而没有错误。

5. 发明授权

US5491790A Power-on sequencing apparatus for initializing and testing a system processing unit 失效
标题翻译：用于初始化和测试系统处理单元的上电排序装置
公开(公告)号：US5491790A
公开(公告)日：1996-02-13
申请号：US231856
申请日：1994-04-22
申请人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr. , Keith L. Petry , Thomas S. Hirsch
发明人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr. , Keith L. Petry , Thomas S. Hirsch
IPC分类号： G06F1/00 , G06F9/06 , G06F9/445 , G06F11/22 , G06F11/267
CPC分类号： G06F11/2236 , G06F11/22 , G06F9/4403
摘要： A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus. Following loading of the peer processor operating system, the EEPROM control circuits, in response to commands from the system bus, enable the microprocessor to address the second region for executing boot routines for loading its operating system.
摘要翻译：除了其他单元之外，处理单元与对等处理器，主存储器共同地耦合到系统总线，并且包括紧密耦合到也可从这样的总线访问的本地存储器的微处理器。处理单元还包括可寻址的电可擦除可编程只读存储器（EEPROM）单元，其耦合到微处理器和系统总线。 EEPROM单元存储在第一和第二分离区域中，两者分别占据通常分配用于存储微处理器引导代码，车载诊断（OBD）例程和操作系统引导例程的相同地址空间。 EEPROM控制电路在上电时，使EEPROM单元处理第一个区域以执行OBD例程，以验证处理单元是否正常工作，包括正确向连接到系统总线的单元发出命令的能力。在加载对等处理器操作系统之后，响应于来自系统总线的命令，EEPROM控制电路使得微处理器能够寻址用于执行用于加载其操作系统的引导例程的第二区域。

6. 发明授权

US5341501A Processor bus access 失效
标题翻译：处理器总线访问
公开(公告)号：US5341501A
公开(公告)日：1994-08-23
申请号：US771582
申请日：1991-10-04
申请人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr.
发明人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr.
IPC分类号： G06F13/368 , G06F9/46
CPC分类号： G06F13/368
摘要： A high performance microprocessor bus state machine couples to a synchronous local bus in common with another state machine for accessing a local memory according to a preestablished bus protocol. Circuit means cosines the state of a predetermined protocol bus signal indicating the release of the local bus and transitions of the clock signal which are not used for synchronizing the operations of the state machines. The resulting signal applies required address and control signals in advance to the local bus enabling the non-microprocessor state machine to generate the required address strobe to local memory on the next clock which follows the release of the local bus by the microprocessor which eliminates a clock cycle whenever local bus control passes from the microprocessor bus state machine to another state machine.
摘要翻译：高性能微处理器总线状态机根据预先建立的总线协议与另一状态机共同连接到同步局部总线，用于访问本地存储器。电路意味着使指示本地总线的释放和不用于同步状态机的操作的时钟信号的转换的预定的协议总线信号的状态。所产生的信号预先将所需的地址和控制信号施加到本地总线，使得非微处理器状态机能够在微处理器释放本地总线之后的下一个时钟产生所需的地址选通脉冲，从而消除时钟当本地总线控制从微处理器总线状态机传递到另一状态机时，循环。

7. 发明授权

US4077565A Error detection and correction locator circuits 失效
标题翻译：误差检测和校正定位电路
公开(公告)号：US4077565A
公开(公告)日：1978-03-07
申请号：US727820
申请日：1976-09-29
申请人： Chester M. Nibby, Jr. , George J. Barlow
发明人： Chester M. Nibby, Jr. , George J. Barlow
IPC分类号： G06F11/10 , H03M13/19 , G11C29/00 , G06F11/12
CPC分类号： G06F11/1048 , H03M13/19
摘要： A main memory system includes encoder and decoder circuits. The encoder circuits are connected to receive data bits and parity bits and from them generate check code bits which are stored with the data bits during a write cycle of operation. The decoder circuits are connected to receive data and check bits read out from memory during a read cycle of operation. The decoder circuits include a plurality of decoder circuits and error locator circuits. Circuits via exclusive OR circuits generate a number of syndrome bit signals. These signals are divided into first and second groups. The first group is coded to specify which one of a number of decoder circuits comprising the error locator circuits is to be enabled in the case of an error condition. The second group of signals is coded to designate the particular data bit to be corrected by the decoder circuits. Predetermined output terminals of each of the decoder circuits representative of valid single bit data error conditions are applied to a plurality of correction circuits for modification of the data signals as specified by the decoder circuits. Additionally, signals from predetermined output terminals of certain ones of the decoder circuits representative of certain single check code bit error conditions are utilized for providing the correct parity for the data signals associated therewith.
摘要翻译：主存储器系统包括编码器和解码器电路。编码器电路被连接以接收数据位和奇偶校验位，并且从它们产生在操作的写周期期间与数据位一起存储的校验码位。在操作的读取周期期间，解码器电路被连接以接收从存储器读出的数据和校验位。解码器电路包括多个解码器电路和误差定位器电路。通过异或电路的电路产生多个校正子位信号。这些信号被分成第一组和第二组。第一组被编码以指定在错误状况的情况下启用包括错误定位器电路的多个解码器电路中的哪一个。第二组信号被编码以指定由解码器电路校正的特定数据位。代表有效的单位数据错误条件的每个解码器电路的预定输出端子被施加到由解码器电路指定的用于修改数据信号的多个校正电路。此外，代表某些单个校验码位错误条件的某些解码器电路的来自预定输出端的信号被用于为与其相关联的数据信号提供正确的奇偶校验。

8. 发明授权

US4072853A Apparatus and method for storing parity encoded data from a plurality of input/output sources 失效
标题翻译：用于存储来自多个输入/输出源的奇偶校验编码数据的装置和方法
公开(公告)号：US4072853A
公开(公告)日：1978-02-07
申请号：US727821
申请日：1976-09-29
申请人： George J. Barlow , Chester M. Nibby, Jr.
发明人： George J. Barlow , Chester M. Nibby, Jr.
IPC分类号： G06F11/10 , G11C29/00 , G06F11/12
CPC分类号： G06F11/1024 , G06F11/1056
摘要： Apparatus and method are included in the main memory of the data processing system which receives data from a plurality of input/output devices connected to a common bus. During a write cycle of operation, a device applies a plurality of data byte signals together with associated parity bits for writing into an addressed storage location of memory. Error detection and correction encoder circuits are connected to receive the data bits and parity bits and from them generate check code bits which are coded to signal selectively the presence of an uncorrectable error condition in accordance with the parity bits from a given source. During a read cycle of operation, error detection and correction decoder circuits connected to the memory in response to the data and check code bits read out from an addressed location are operative to generate a number of syndrome bits having a predetermined characteristic for indicating the existence of an uncorrectable error condition when the parity bits associated with data signals when written originally into memory if checked would have indicated that the data was in error.
摘要翻译：数据处理系统的主存储器中包括装置和方法，该数据处理系统从连接到公共总线的多个输入/输出装置接收数据。在操作的写周期期间，设备将多个数据字节信号与相关联的奇偶校验位一起应用以写入存储器的寻址存储位置。连接错误检测和校正编码器电路以接收数据位和奇偶校验位，并且从它们产生编码的校验码位，以根据来自给定源的奇偶校验位选择性地存在不可校正的错误状况。在操作的读取周期期间，响应于从寻址位置读出的数据和校验码位连接到存储器的错误检测和校正解码器电路可操作以产生具有预定特性的多个校正子位，用于指示存在当与最初写入存储器的数据信号相关联的奇偶校验位如果被检查时，将会出现数据错误的情况，这是一个不可校正的错误状态。

9. 发明授权

US4558429A Pause apparatus for a memory controller with interleaved queuing apparatus 失效
标题翻译：暂停具有交错排队装置的存储器控制器的装置
公开(公告)号：US4558429A
公开(公告)日：1985-12-10
申请号：US331933
申请日：1981-12-17
申请人： George J. Barlow , Chester M. Nibby, Jr. , Robert B. Johnson
发明人： George J. Barlow , Chester M. Nibby, Jr. , Robert B. Johnson
IPC分类号： G06F13/16 , G06F12/00 , G06F13/18 , G06F13/28 , G06F13/32 , G06F9/00
CPC分类号： G06F13/18 , G06F13/28
摘要： A data processing system includes a plurality of memory command generating units which connect to a common bus network with a number of memory subsystems. Each subsystem includes a controller which controls the operation of a number of memory module units and includes a number of queue circuits for storing memory requests to be processed. The memory controller further includes control apparatus connected to monitor bus activity. In response to certain bus activity conditions occurring during multiword transfer operations, the control apparatus operates to lengthen the time between successive multiword transfers of data to the bus so as to ensure that new requestors having lower priorities than a memory controller gain access to an available queue notwithstanding the amount of bus delay incurred in transmitting their memory requests.
摘要翻译：数据处理系统包括多个存储器命令生成单元，其连接到具有多个存储器子系统的公共总线网络。每个子系统包括控制多个存储器模块单元的操作的控制器，并且包括用于存储要处理的存储器请求的多个队列电路。存储器控制器还包括连接到监视总线活动的控制装置。响应于在多字传输操作期间发生的某些总线活动条件，控制装置操作以将数据的连续多字传输之间的时间延长到总线，以便确保具有比存储器控制器低的优先级的新请求者获得对可用队列的访问尽管在发送其内存请求时发生总线延迟的数量。

10. 发明授权

US5956522A Symmetric multiprocessing system with unified environment and distributed system functions 失效
公开(公告)号：US5956522A
公开(公告)日：1999-09-21
申请号：US405510
申请日：1995-03-16
申请人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F Joyce , Martin Massucci , Lance T. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
发明人： James F. Bertone , Bruno DiPlacido, Jr. , Thomas F Joyce , Martin Massucci , Lance T. McNally , Thomas L. Murray, Jr. , Chester M. Nibby, Jr. , Michelle A. Pence , Marc Sanfacon , Jian-Kuo Shen , Jeffrey S. Somers , G. Lewis Steiner
IPC分类号： G06F12/08 , G06F13/16 , G06F13/368 , G06F13/00
CPC分类号： G06F13/1657 , G06F12/0831 , G06F13/1689 , G06F13/1694 , G06F13/368
摘要： A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

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