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1. 发明申请

US20120043982A1 CRITICAL PATH MONITOR HAVING SELECTABLE OPERATING MODES AND SINGLE EDGE DETECTION 有权
标题翻译：具有选择性操作模式和单边缘检测的关键路径监视器
公开(公告)号：US20120043982A1
公开(公告)日：2012-02-23
申请号：US12861289
申请日：2010-08-23
申请人： Gary D. Carpenter , Alan J. Drake , Michael S. Floyd , Robert M. Senger
发明人： Gary D. Carpenter , Alan J. Drake , Michael S. Floyd , Robert M. Senger
IPC分类号： G01R31/3187
CPC分类号： G01R31/31725
摘要： A critical path monitor having selectable data output modes provides additional information about critical path delay variation. A pulse is propagated through a synthesized path representing a critical path in a functional logic circuit and a synthesized path delay is measured by a monitoring circuit that detects the arrival of an edge of the pulse at the output of the synthesized delay. The measured delay is provided as a real-time output and a processed result of the measured delay is processed according to a data output mode selected from multiple selectable output modes, thereby providing different information describing the real-time data about critical path delay, such as a range of edge positions corresponding to a variation of the critical path delay.
摘要翻译：具有可选数据输出模式的关键路径监视器提供关于关键路径延迟变化的附加信息。脉冲通过表示功能逻辑电路中的关键路径的合成路径传播，合成路径延迟由检测脉冲边缘在合成延迟的输出处的监控电路测量。测量的延迟被提供为实时输出，并且根据从多个可选输出模式中选择的数据输出模式来处理测量的延迟的处理结果，从而提供描述关于关键路径延迟的实时数据的不同信息，例如作为对应于关键路径延迟的变化的边缘位置的范围。

2. 发明申请

US20080104561A1 Circuit for Dynamic Circuit Timing Synthesis and Monitoring of Critical Paths and Environmental Conditions of an Integrated Circuit 失效
标题翻译：用于动态电路定时的电路综合和监控集成电路的关键路径和环境条件
公开(公告)号：US20080104561A1
公开(公告)日：2008-05-01
申请号：US11549138
申请日：2006-10-13
申请人： Gary D. Carpenter , Alan J. Drake , Harmander S. Deogun , Michael S. Floyd , Norman K. James , Robert M. Senger
发明人： Gary D. Carpenter , Alan J. Drake , Harmander S. Deogun , Michael S. Floyd , Norman K. James , Robert M. Senger
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036
摘要： A circuit for dynamically monitoring the operation of an integrated circuit under differing temperature, frequency, and voltage (including localized noise and droop), and for detecting early life wear-out mechanisms (e.g., NBTI, hot electrons).
摘要翻译：用于在不同的温度，频率和电压（包括局部噪声和下垂）下动态地监测集成电路的操作以及用于检测早期寿命磨损机制（例如，NBTI，热电子）的电路。

3. 发明授权

US08405413B2 Critical path monitor having selectable operating modes and single edge detection 有权
标题翻译：关键路径监视器具有可选择的操作模式和单边缘检测
公开(公告)号：US08405413B2
公开(公告)日：2013-03-26
申请号：US12861289
申请日：2010-08-23
申请人： Gary D. Carpenter , Alan J. Drake , Michael S. Floyd , Robert M. Senger
发明人： Gary D. Carpenter , Alan J. Drake , Michael S. Floyd , Robert M. Senger
IPC分类号： G01R31/3187
CPC分类号： G01R31/31725
摘要： A critical path monitor having selectable data output modes provides additional information about critical path delay variation. A pulse is propagated through a synthesized path representing a critical path in a functional logic circuit and a synthesized path delay is measured by a monitoring circuit that detects the arrival of an edge of the pulse at the output of the synthesized delay. The measured delay is provided as a real-time output and a processed result of the measured delay is processed according to a data output mode selected from multiple selectable output modes, thereby providing different information describing the real-time data about critical path delay, such as a range of edge positions corresponding to a variation of the critical path delay.
摘要翻译：具有可选数据输出模式的关键路径监视器提供关于关键路径延迟变化的附加信息。脉冲通过表示功能逻辑电路中的关键路径的合成路径传播，合成路径延迟由检测脉冲边缘在合成延迟的输出处的监控电路测量。测量的延迟被提供为实时输出，并且根据从多个可选输出模式中选择的数据输出模式来处理测量的延迟的处理结果，从而提供描述关于关键路径延迟的实时数据的不同信息，例如作为对应于关键路径延迟的变化的边缘位置的范围。

4. 发明授权

US07576569B2 Circuit for dynamic circuit timing synthesis and monitoring of critical paths and environmental conditions of an integrated circuit 失效
标题翻译：用于动态电路定时合成和监控集成电路的关键路径和环境条件的电路
公开(公告)号：US07576569B2
公开(公告)日：2009-08-18
申请号：US11549138
申请日：2006-10-13
申请人： Gary D. Carpenter , Alan J. Drake , Harmander S. Deogun , Michael S. Floyd , Norman K. James , Robert M. Senger
发明人： Gary D. Carpenter , Alan J. Drake , Harmander S. Deogun , Michael S. Floyd , Norman K. James , Robert M. Senger
IPC分类号： G01R29/02 , G06F17/50 , H03K5/22
CPC分类号： G06F17/5031 , G06F17/5036
摘要： A circuit for dynamically monitoring the operation of an integrated circuit under differing temperature, frequency, and voltage (including localized noise and droop), and for detecting early life wear-out mechanisms (e.g., NBTI, hot electrons).
摘要翻译：用于在不同的温度，频率和电压（包括局部噪声和下垂）下动态地监测集成电路的操作以及用于检测早期寿命磨损机制（例如，NBTI，热电子）的电路。

5. 发明授权

US07548823B2 Correction of delay-based metric measurements using delay circuits having differing metric sensitivities 失效
标题翻译：使用具有不同度量灵敏度的延迟电路校正基于延迟的度量测量
公开(公告)号：US07548823B2
公开(公告)日：2009-06-16
申请号：US11750385
申请日：2007-05-18
申请人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
发明人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
IPC分类号： G01R29/00
CPC分类号： G01R31/3016
摘要： Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature. Temperature results can then be corrected for supply voltage variation and vice-versa.
摘要翻译：使用具有不同的度量灵敏度的延迟电路对基于延迟的度量测量进行校正为使用延迟线的环境和其他电路量度测量提供了改进的精度。可以使用对测量的特定度量具有不同灵敏度的至少两个延迟线来同时或顺序地执行可以是单次测量或环形振荡器频率测量的延迟线测量。校正电路或算法使用测量的延迟或环形振荡器频率，并根据其他延迟或环形振荡器频率来校正从延迟或环形振荡器频率之一确定的度量测量中的至少一个。延迟可以是逆变器链，一个链对电源电压的敏感性高于另一个延迟链，另一个延迟链对温度具有较高的灵敏度。然后可以对电源电压变化校正温度结果，反之亦然。

6. 发明申请

US20090144006A1 CALIBRATION OF MULTI-METRIC SENSITIVE DELAY MEASUREMENT CIRCUITS 审中-公开
标题翻译：多维敏感延迟测量电路校准
公开(公告)号：US20090144006A1
公开(公告)日：2009-06-04
申请号：US12367893
申请日：2009-02-09
申请人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
发明人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
IPC分类号： G01R29/00
CPC分类号： G01R31/2874 , G01R31/3016
摘要： A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.
摘要翻译：用于校准多度量敏感延迟测量电路的方法和系统提供减少延迟中的过程相关变化及其对电路度量的敏感性。用于延迟电路的处理角由至少一个延迟测量确定，对于该延迟测量，由于过程变化引起的延迟的变化被预先表征。延迟测量是在已知的温度，电源电压和延迟电路设计测量的任何其他环境度量的已知值进行的。然后从建立的过程角确定延迟与电路度量的系数，从而延迟测量的电路度量值的计算由于电路到电路和/或管芯到管芯的工艺变化而提高了精度和减小的变化的延迟电路。

7. 发明申请

US20080288197A1 Calibration of Multi-Metric Sensitive Delay Measurement Circuits 有权
标题翻译：多尺度敏感延迟测量电路的校准
公开(公告)号：US20080288197A1
公开(公告)日：2008-11-20
申请号：US11750475
申请日：2007-05-18
申请人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
发明人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
IPC分类号： G01R29/02
CPC分类号： G01R31/2874 , G01R31/3016
摘要： A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.
摘要翻译：用于校准多度量敏感延迟测量电路的方法和系统提供减少延迟中的过程相关变化及其对电路度量的敏感性。用于延迟电路的处理角由至少一个延迟测量确定，对于该延迟测量，由于过程变化引起的延迟的变化被预先表征。延迟测量是在已知的温度，电源电压和延迟电路设计测量的任何其他环境度量的已知值进行的。然后从建立的过程角确定延迟与电路度量的系数，从而延迟测量的电路度量值的计算由于电路到电路和/或管芯到管芯的工艺变化而提高了精度和减小的变化的延迟电路。

8. 发明申请

US20080288196A1 Correction of Delay-Based Metric Measurements Using Delay Circuits Having Differing Metric Sensitivities 失效
标题翻译：使用具有不同公制灵敏度的延迟电路校正基于延迟的公制测量
公开(公告)号：US20080288196A1
公开(公告)日：2008-11-20
申请号：US11750385
申请日：2007-05-18
申请人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
发明人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
IPC分类号： G01R29/00 , G01R29/02
CPC分类号： G01R31/3016
摘要： Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature. Temperature results can then be corrected for supply voltage variation and vice-versa.
摘要翻译：使用具有不同的度量灵敏度的延迟电路对基于延迟的度量测量进行校正为使用延迟线的环境和其他电路量度测量提供了改进的精度。可以使用对测量的特定度量具有不同灵敏度的至少两个延迟线来同时或顺序地执行可以是单次测量或环形振荡器频率测量的延迟线测量。校正电路或算法使用测量的延迟或环形振荡器频率，并根据其他延迟或环形振荡器频率来校正从延迟或环形振荡器频率之一确定的度量测量中的至少一个。延迟可以是逆变器链，一个链对电源电压的敏感性高于另一个延迟链，另一个延迟链对温度具有较高的灵敏度。然后可以对电源电压变化校正温度结果，反之亦然。

9. 发明授权

US07542862B2 Calibration of multi-metric sensitive delay measurement circuits 有权
标题翻译：多尺度敏感延迟测量电路的校准
公开(公告)号：US07542862B2
公开(公告)日：2009-06-02
申请号：US11750475
申请日：2007-05-18
申请人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
发明人： Harmander Singh , Alan J. Drake , Fadi H. Gebara , John P. Keane , Jeremy D. Schaub , Robert M. Senger
IPC分类号： G01R29/02 , G01R29/00 , G01R35/00 , G01D18/00 , G01P21/00
CPC分类号： G01R31/2874 , G01R31/3016
摘要： A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.
摘要翻译：用于校准多度量敏感延迟测量电路的方法和系统提供减少延迟中的过程相关变化及其对电路度量的敏感性。用于延迟电路的处理角由至少一个延迟测量确定，对于该延迟测量，由于过程变化引起的延迟的变化被预先表征。延迟测量是在已知的温度，电源电压和延迟电路设计测量的任何其他环境度量的已知值进行的。然后从建立的过程角确定延迟与电路度量的系数，从而延迟测量的电路度量值的计算由于电路到电路和/或管芯到管芯的工艺变化而提高了精度和减小的变化的延迟电路。

10. 发明授权

US09037669B2 Remote processing and memory utilization 有权
标题翻译：远程处理和内存利用
公开(公告)号：US09037669B2
公开(公告)日：2015-05-19
申请号：US13570916
申请日：2012-08-09
申请人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F15/167 , G06F15/173 , G06F11/00 , G06F9/54 , H04L29/06
CPC分类号： G06F9/547 , H04L29/0617 , H04L67/40
摘要： According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.
摘要翻译：根据本发明的一个实施例，一种用于操作存储器的系统包括由网络耦合到第二节点的第一节点，所述系统被配置为执行一种方法，该方法包括从所述第二节点接收来自所述第二节点的处理元件中的所述远程事务消息第一节点经由网络，其中当所述远程事务消息被传送到所述处理元件时，所述远程事务消息绕过所述第一节点中的主处理器。此外，该方法包括基于远程事务消息，由处理元件访问来自第一节点中的存储器中的位置的数据，以及由处理元件基于数据和远程事务消息执行计算。

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