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1. 发明申请

US20060179290A1 System and method for creating precise exceptions 失效
标题翻译：用于创建精确异常的系统和方法
公开(公告)号：US20060179290A1
公开(公告)日：2006-08-10
申请号：US11055193
申请日：2005-02-10
申请人： Fadi Busaba , Michael Mack , John Rell , Eric Schwarz , Chung-Lung Shum , Timothy Slegel , Scott Swaney , Sheryll Veneracion
发明人： Fadi Busaba , Michael Mack , John Rell , Eric Schwarz , Chung-Lung Shum , Timothy Slegel , Scott Swaney , Sheryll Veneracion
IPC分类号： G06F9/44
CPC分类号： G06F9/4812 , G06F9/30101 , G06F9/3863 , G06F2209/481
摘要： A method for creating precise exceptions including checkpointing an exception causing instruction. The checkpointing results in a current checkpointed state. The current checkpointed state is locked. It is determined if any of a plurality of registers require restoration to the current checkpointed state. One or more of the registers are restored to the current checkpointed state in response to the results of the determining indicating that the one or more registers require the restoring. The execution unit is restarted at the exception handler or the next sequential instruction dependent on whether traps are enabled for the exception.
摘要翻译：一种用于创建精确异常的方法，包括检查指向引起异常的指令。检查点导致当前检查点状态。当前检查点状态被锁定。确定多个寄存器中的任一个是否需要恢复到当前检查点状态。响应于指示一个或多个寄存器需要恢复的确定结果，一个或多个寄存器恢复到当前检查点状态。执行单元在异常处理程序或下一个顺序指令下重新启动，取决于是否为异常启用陷阱。

2. 发明申请

US20070233773A1 MODULAR BINARY MULTIPLIER FOR SIGNED AND UNSIGNED OPERANDS OF VARIABLE WIDTHS 有权
标题翻译：用于可变宽度的签名和不相关操作的模块化二进制多路复用器
公开(公告)号：US20070233773A1
公开(公告)日：2007-10-04
申请号：US11749224
申请日：2007-05-16
申请人： Fadi Busaba , Steven Carlough , David Hutton , Christopher Krygowski , John Rell , Sheryll Veneracion
发明人： Fadi Busaba , Steven Carlough , David Hutton , Christopher Krygowski , John Rell , Sheryll Veneracion
IPC分类号： G06F7/44
CPC分类号： G06F7/5324 , G06F7/5332 , G06F9/30014 , G06F2207/3816
摘要： A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in communication with the execution unit and another register of the first pipeline; a second pipeline, a second execution unit, and a second multiplexer; a rotator in communication with one register of the second pipeline and the second execution unit; and a leading zero detection register in communication with the second execution unit and another register of the first pipeline; and a third pipeline, a binary multiplier in communication with a pair registers of the third pipeline; a general register; an operand buffer for obtaining first and second operands; and a bus for communication between the pipelines, the general register and the operand buffer.
摘要翻译：超标量处理器中的二进制乘法系统包括第一流水线，执行单元和第一多路复用器; 与第一流水线和执行单元的一个寄存器通信的第一旋转器; 以及与执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 第二管线，第二执行单元和第二多路复用器; 与所述第二管线的一个寄存器和所述第二执行单元通信的转动器; 以及与第二执行单元和第一管道的另一个寄存器通信的前导零检测寄存器; 以及第三管线，与所述第三管道的对寄存器通信的二进制乘法器; 一般登记册; 用于获得第一和第二操作数的操作数缓冲器; 和一条总线，用于管道，通用寄存器和操作数缓冲区之间的通信。

3. 发明申请

US20070214205A1 MODULAR BINARY MULTIPLIER FOR SIGNED AND UNSIGNED OPERANDS OF VARIABLE WIDTHS 有权
标题翻译：用于可变宽度的签名和不相关操作的模块化二进制多路复用器
公开(公告)号：US20070214205A1
公开(公告)日：2007-09-13
申请号：US11749239
申请日：2007-05-16
申请人： Fadi Busaba , Steven Carlough , David Hutton , Christopher Krygowski , John Rell , Sheryll Veneracion
发明人： Fadi Busaba , Steven Carlough , David Hutton , Christopher Krygowski , John Rell , Sheryll Veneracion
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F7/5332 , G06F9/30014 , G06F2207/3816
摘要： A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgroups; in the event the multiplicand is larger than a selected length, partitioning the multiplicand into a plurality of multiplicand subgroups and at least one of zeroing out of unused bits of the multiplicand subgroup and sign-extending a smaller portion of the multiplicand subgroup; establishing a plurality of multiplicand multiples based on at least one of a selected multiplicand subgroup of the plurality of multiplicand subgroups and the multiplicand; selecting one or more of the multiplicand multiples of the plurality of multiplicand multiples based on the each multiplier subgroup of the plurality of multiplier subgroups; and generating a first modular product based on the selected multiplicand multiples.
摘要翻译：在处理设备中实现二进制乘法的方法包括从存储设备获取乘法器和乘法器; 在乘数大于选定长度的情况下，将乘法器分成多个乘法器子组; 在所述被乘数大于所选择的长度的情况下，将所述被乘数划分为多个被乘数的子组和被乘数子组的未使用的比特中的至少一个，并对被乘数子组的较小部分进行符号扩展; 基于所述多个被乘数子组和被乘数中的所选择的被乘数子群中的至少一个，建立多个被乘数; 基于所述多个乘法器子组中的每个乘法器子组来选择所述多个被乘数中的一个或多个被乘数; 以及基于所选择的被乘数生成第一模块化产品。

4. 发明申请

US20070061388A1 System and method for converting from scaled binary coded decimal into decimal floating point 有权
标题翻译：从缩放二进制编码十进制转换为十进制浮点的系统和方法
公开(公告)号：US20070061388A1
公开(公告)日：2007-03-15
申请号：US11227515
申请日：2005-09-15
申请人： Steven Carlough , Eric Schwarz , Sheryll Veneracion
发明人： Steven Carlough , Eric Schwarz , Sheryll Veneracion
IPC分类号： G06F7/00
CPC分类号： H03M7/24 , H03M7/04
摘要： A system and method for converting from scaled binary coded decimal (SBCD) into decimal floating point (DFP). The system includes a mechanism for receiving one or more of an exponent part of a SBCD number and a coefficient part of the SBCD number. The system also includes at least one of a mechanism for performing coefficient compression on the coefficient part of the SBCD number to create a coefficient part of a DFP number and a mechanism for performing exponent insertion including inserting the exponent part of the SBCD number into an exponent part of the DFP number.
摘要翻译：从缩放二进制编码十进制（SBCD）转换为十进制浮点（DFP）的系统和方法。该系统包括用于接收SBCD号的指数部分和SBCD号的系数部分中的一个或多个的机构。该系统还包括用于对SBCD号码的系数部分执行系数压缩以创建DFP号码的系数部分的机制和用于执行指数插入的机制中的至少一个，包括将SBCD号码的指数部分插入指数 DFP编号的一部分。

5. 发明申请

US20070061387A1 System and method for converting from decimal floating point into scaled binary coded decimal 有权
标题翻译：从十进制浮点转换为二进制编码十进制的系统和方法
公开(公告)号：US20070061387A1
公开(公告)日：2007-03-15
申请号：US11227481
申请日：2005-09-15
申请人： Steven Carlough , Eric Schwarz , Sheryll Veneracion
发明人： Steven Carlough , Eric Schwarz , Sheryll Veneracion
IPC分类号： G06F7/00
CPC分类号： H03M7/24 , H03M7/12
摘要： A system and method for converting from decimal floating point (DFP) into scaled binary coded decimal (SBCD). The system includes a mechanism for receiving a DFP number. The system also includes at least one of a mechanism for performing coefficient expansion on the DFP number to create a binary coded decimal (BCD) coefficient part of a SBCD number and a mechanism for performing exponent extraction on the DFP number to create an exponent part of the SBCD number.
摘要翻译：用于从十进制浮点（DFP）转换为缩放二进制编码十进制（SBCD）的系统和方法。该系统包括用于接收DFP号码的机制。该系统还包括用于在DFP号码上执行系数扩展以创建SBCD号码的二进制编码十进制（BCD）系数部分的机制中的至少一个以及用于在DFP号码上执行指数提取以创建指数部分的机构 SBCD号码。

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