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1. 发明授权

US07843747B2 System and method for better testability of OTP memory 有权
标题翻译： OTP内存的更好的可测试性的系统和方法
公开(公告)号：US07843747B2
公开(公告)日：2010-11-30
申请号：US12124989
申请日：2008-05-21
申请人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang , Po-Hung Chen
发明人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang , Po-Hung Chen
IPC分类号： G11C29/00
CPC分类号： G11C29/08 , G11C2216/26
摘要： A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory.
摘要翻译：公开了一种用于测试在具有存储器单元阵列的一次可编程（OTP）存储器中执行写入和读取操作的逻辑电路的系统，该系统包括具有与整个存储器单元相同数量的单元格的测试单元列存储单元阵列的列，一行具有与存储器单元阵列的整行相同数量的单元的测试单元，其中测试单元的列和行首先被写入然后从在测试操作期间，并且在OTP存储器的非测试操作期间永远不能被访问。

2. 发明申请

US20090141573A1 System and Method for Better Testability of OTP Memory 有权
标题翻译： OTP内存的可测试性的系统和方法
公开(公告)号：US20090141573A1
公开(公告)日：2009-06-04
申请号：US12124989
申请日：2008-05-21
申请人： Fu Lung Hsueh , Shine Chung , Wen-Kuan Fang , Po-Hung Chen
发明人： Fu Lung Hsueh , Shine Chung , Wen-Kuan Fang , Po-Hung Chen
IPC分类号： G11C29/00
CPC分类号： G11C29/08 , G11C2216/26
摘要： A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory.
摘要翻译：公开了一种用于测试在具有存储器单元阵列的一次可编程（OTP）存储器中执行写入和读取操作的逻辑电路的系统，该系统包括具有与整个存储器单元相同数量的单元格的测试单元列存储单元阵列的列，一行具有与存储器单元阵列的整行相同数量的单元的测试单元，其中测试单元的列和行首先被写入然后从在测试操作期间，并且在OTP存储器的非测试操作期间永远不能被访问。

3. 发明申请

US20090296448A1 DIODE AS VOLTAGE DOWN CONVERTER FOR OTP HIGH PROGRAMMING VOLTAGE APPLICATIONS 审中-公开
标题翻译：二极管作为低压转换器用于OTP高度编程电压应用
公开(公告)号：US20090296448A1
公开(公告)日：2009-12-03
申请号：US12367455
申请日：2009-02-06
申请人： Fu Lung Hsueh , Shine Chung , Wen-Kuan Fang
发明人： Fu Lung Hsueh , Shine Chung , Wen-Kuan Fang
IPC分类号： G11C17/06 , G11C5/14 , G11C17/00 , G11C7/00
CPC分类号： G11C16/30 , G11C5/00
摘要： A voltage down converter for programming a one-time-programmable (OTP) memory comprising is disclosed, the voltage down converter comprises a bonding pad for coupling to a programming power supply, and at least one forward biased diode coupled between the bonding pad and the OTP memory, wherein a programming voltage received by the OTP memory is lowered from the programming power supply by the voltage drop across the forward biased diode.
摘要翻译：公开了一种用于对一次可编程（OTP）存储器进行编程的降压转换器，所述降压转换器包括用于耦合到编程电源的接合焊盘，以及耦合在所述接合焊盘和所述接合焊盘之间的至少一个正向偏置二极管 OTP存储器，其中由OTP存储器接收的编程电压通过正向偏置二极管上的电压降从编程电源降低。

4. 发明授权

US07782656B2 SRAM with improved read/write stability 有权
标题翻译： SRAM具有改善的读/写稳定性
公开(公告)号：US07782656B2
公开(公告)日：2010-08-24
申请号：US12178420
申请日：2008-07-23
申请人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang
发明人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang
IPC分类号： G11C11/00 , G11C5/06 , G11C7/10
CPC分类号： G11C11/419 , G11C11/412
摘要： A static random access memory (SRAM) cell is disclosed which comprises a cross-couple inverter latch coupled between a positive supply voltage and ground, and having at least a first storage node, and a first and second switching device serially connected between the first storage node and a predetermined voltage source, wherein the first switching device is controlled by a word select signal, and the second switching device is controlled by a first bit select signal, wherein either the word select signal or the first bit select signal is only activated during a write operation.
摘要翻译：公开了一种静态随机存取存储器（SRAM）单元，其包括耦合在正电源电压和地之间并具有至少第一存储节点的交叉耦合逆变器锁存器，以及串联连接在第一存储器节点和预定电压源，其中第一开关装置由字选择信号控制，第二开关装置由第一位选择信号控制，其中字选择信号或第一位选择信号仅在一个写操作。

5. 发明申请

US20100020590A1 SRAM WITH IMPROVED READ/WRITE STABILITY 有权
标题翻译： SRAM具有改进的读/写稳定性
公开(公告)号：US20100020590A1
公开(公告)日：2010-01-28
申请号：US12178420
申请日：2008-07-23
申请人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang
发明人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C11/412
摘要： A static random access memory (SRAM) cell is disclosed which comprises a cross-couple inverter latch coupled between a positive supply voltage and ground, and having at least a first storage node, and a first and second switching device serially connected between the first storage node and a predetermined voltage source, wherein the first switching device is controlled by a word select signal, and the second switching device is controlled by a first bit select signal, wherein either the word select signal or the first bit select signal is only activated during a write operation.
摘要翻译：公开了一种静态随机存取存储器（SRAM）单元，其包括耦合在正电源电压和地之间并具有至少第一存储节点的交叉耦合逆变器锁存器，以及串联连接在第一存储器节点和预定电压源，其中第一开关装置由字选择信号控制，第二开关装置由第一位选择信号控制，其中字选择信号或第一位选择信号仅在一个写操作。

6. 发明授权

US06442054B1 Sense amplifier for content addressable memory 失效
标题翻译：用于内容可寻址存储器的感应放大器
公开(公告)号：US06442054B1
公开(公告)日：2002-08-27
申请号：US09866056
申请日：2001-05-24
申请人： Allen L. Evans , Wen-Kuan Fang
发明人： Allen L. Evans , Wen-Kuan Fang
IPC分类号： G11C1500
CPC分类号： G11C7/062 , G11C15/04
摘要： A sense amplifier includes a first transistor coupled between a match line of a CAM array and a VDD supply terminal. The match line is pre-charged through the first transistor to a voltage equal to a reference voltage minus the first transistor threshold voltage, VT1. The match line is coupled to the source of a second transistor, which has a threshold voltage VT2, wherein VT2>VT1. A dummy line of the CAM array, which is coupled to the gate of the second transistor, is pre-charged to the reference voltage. A storage node, which is coupled to the drain of the second transistor, is pre-charged to the VDD supply voltage. A non-match condition causes the voltage on the match line to be pulled down. When the voltage on the dummy line exceeds the voltage on the match line by VT2, the second transistor turns on, thereby pulling down the storage node.
摘要翻译：读出放大器包括耦合在CAM阵列的匹配线和VDD电源端之间的第一晶体管。匹配线通过第一晶体管预充电到等于参考电压减去第一晶体管阈值电压VT1的电压。匹配线耦合到具有阈值电压VT2的第二晶体管的源极，其中VT2> VT1。耦合到第二晶体管的栅极的CAM阵列的虚拟线被预充电到参考电压。耦合到第二晶体管的漏极的存储节点被预充电到VDD电源电压。不匹配条件导致匹配线上的电压被拉低。当虚线上的电压超过匹配线上的电压VT2时，第二晶体管导通，从而拉下存储节点。

7. 发明授权

US6037807A Synchronous sense amplifier with temperature and voltage compensated translator 失效
标题翻译：具有温度和电压补偿转换器的同步读出放大器
公开(公告)号：US6037807A
公开(公告)日：2000-03-14
申请号：US80710
申请日：1998-05-18
申请人： Chau-Chin Wu , Ta-Ke Tien , Wen-Kuan Fang
发明人： Chau-Chin Wu , Ta-Ke Tien , Wen-Kuan Fang
IPC分类号： G11C7/06 , H01L35/00
CPC分类号： G11C7/06
摘要： A bias control circuit for controlling the bias current in a sense amplifier circuit. The bias control circuit maintains a substantially constant bias current when the V.sub.CC supply voltage decreases, thereby maintaining the operating speed of the sense amplifier circuit at a predetermined level. The bias control circuit also increases the bias current as the temperature of the sense amplifier circuit increases, thereby maintaining the operating speed of the sense amplifier circuit at the predetermined level. Furthermore, the bias circuit controls the logic low voltage provided by the sense amplifier circuit to be less than a predetermined threshold value, even as the V.sub.CC supply voltage increases.
摘要翻译：用于控制读出放大器电路中的偏置电流的偏置控制电路。当VCC电源电压降低时，偏置控制电路保持基本恒定的偏置电流，从而将读出放大器电路的工作速度保持在预定的水平。当感测放大器电路的温度升高时，偏置控制电路也增加偏置电流，从而将读出放大器电路的工作速度保持在预定的水平。此外，即使VCC电源电压增加，偏置电路将由读出放大器电路提供的逻辑低电压控制为小于预定阈值。

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