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1. 发明授权

US07843747B2 System and method for better testability of OTP memory 有权
标题翻译： OTP内存的更好的可测试性的系统和方法
公开(公告)号：US07843747B2
公开(公告)日：2010-11-30
申请号：US12124989
申请日：2008-05-21
申请人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang , Po-Hung Chen
发明人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang , Po-Hung Chen
IPC分类号： G11C29/00
CPC分类号： G11C29/08 , G11C2216/26
摘要： A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory.
摘要翻译：公开了一种用于测试在具有存储器单元阵列的一次可编程（OTP）存储器中执行写入和读取操作的逻辑电路的系统，该系统包括具有与整个存储器单元相同数量的单元格的测试单元列存储单元阵列的列，一行具有与存储器单元阵列的整行相同数量的单元的测试单元，其中测试单元的列和行首先被写入然后从在测试操作期间，并且在OTP存储器的非测试操作期间永远不能被访问。

2. 发明申请

US20090141573A1 System and Method for Better Testability of OTP Memory 有权
标题翻译： OTP内存的可测试性的系统和方法
公开(公告)号：US20090141573A1
公开(公告)日：2009-06-04
申请号：US12124989
申请日：2008-05-21
申请人： Fu Lung Hsueh , Shine Chung , Wen-Kuan Fang , Po-Hung Chen
发明人： Fu Lung Hsueh , Shine Chung , Wen-Kuan Fang , Po-Hung Chen
IPC分类号： G11C29/00
CPC分类号： G11C29/08 , G11C2216/26
摘要： A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory.
摘要翻译：公开了一种用于测试在具有存储器单元阵列的一次可编程（OTP）存储器中执行写入和读取操作的逻辑电路的系统，该系统包括具有与整个存储器单元相同数量的单元格的测试单元列存储单元阵列的列，一行具有与存储器单元阵列的整行相同数量的单元的测试单元，其中测试单元的列和行首先被写入然后从在测试操作期间，并且在OTP存储器的非测试操作期间永远不能被访问。

3. 发明申请

US20090296448A1 DIODE AS VOLTAGE DOWN CONVERTER FOR OTP HIGH PROGRAMMING VOLTAGE APPLICATIONS 审中-公开
标题翻译：二极管作为低压转换器用于OTP高度编程电压应用
公开(公告)号：US20090296448A1
公开(公告)日：2009-12-03
申请号：US12367455
申请日：2009-02-06
申请人： Fu Lung Hsueh , Shine Chung , Wen-Kuan Fang
发明人： Fu Lung Hsueh , Shine Chung , Wen-Kuan Fang
IPC分类号： G11C17/06 , G11C5/14 , G11C17/00 , G11C7/00
CPC分类号： G11C16/30 , G11C5/00
摘要： A voltage down converter for programming a one-time-programmable (OTP) memory comprising is disclosed, the voltage down converter comprises a bonding pad for coupling to a programming power supply, and at least one forward biased diode coupled between the bonding pad and the OTP memory, wherein a programming voltage received by the OTP memory is lowered from the programming power supply by the voltage drop across the forward biased diode.
摘要翻译：公开了一种用于对一次可编程（OTP）存储器进行编程的降压转换器，所述降压转换器包括用于耦合到编程电源的接合焊盘，以及耦合在所述接合焊盘和所述接合焊盘之间的至少一个正向偏置二极管 OTP存储器，其中由OTP存储器接收的编程电压通过正向偏置二极管上的电压降从编程电源降低。

4. 发明授权

US07782656B2 SRAM with improved read/write stability 有权
标题翻译： SRAM具有改善的读/写稳定性
公开(公告)号：US07782656B2
公开(公告)日：2010-08-24
申请号：US12178420
申请日：2008-07-23
申请人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang
发明人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang
IPC分类号： G11C11/00 , G11C5/06 , G11C7/10
CPC分类号： G11C11/419 , G11C11/412
摘要： A static random access memory (SRAM) cell is disclosed which comprises a cross-couple inverter latch coupled between a positive supply voltage and ground, and having at least a first storage node, and a first and second switching device serially connected between the first storage node and a predetermined voltage source, wherein the first switching device is controlled by a word select signal, and the second switching device is controlled by a first bit select signal, wherein either the word select signal or the first bit select signal is only activated during a write operation.
摘要翻译：公开了一种静态随机存取存储器（SRAM）单元，其包括耦合在正电源电压和地之间并具有至少第一存储节点的交叉耦合逆变器锁存器，以及串联连接在第一存储器节点和预定电压源，其中第一开关装置由字选择信号控制，第二开关装置由第一位选择信号控制，其中字选择信号或第一位选择信号仅在一个写操作。

5. 发明申请

US20100020590A1 SRAM WITH IMPROVED READ/WRITE STABILITY 有权
标题翻译： SRAM具有改进的读/写稳定性
公开(公告)号：US20100020590A1
公开(公告)日：2010-01-28
申请号：US12178420
申请日：2008-07-23
申请人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang
发明人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C11/412
摘要： A static random access memory (SRAM) cell is disclosed which comprises a cross-couple inverter latch coupled between a positive supply voltage and ground, and having at least a first storage node, and a first and second switching device serially connected between the first storage node and a predetermined voltage source, wherein the first switching device is controlled by a word select signal, and the second switching device is controlled by a first bit select signal, wherein either the word select signal or the first bit select signal is only activated during a write operation.
摘要翻译：公开了一种静态随机存取存储器（SRAM）单元，其包括耦合在正电源电压和地之间并具有至少第一存储节点的交叉耦合逆变器锁存器，以及串联连接在第一存储器节点和预定电压源，其中第一开关装置由字选择信号控制，第二开关装置由第一位选择信号控制，其中字选择信号或第一位选择信号仅在一个写操作。

6. 发明授权

US08258602B2 Bipolar junction transistors having a fin 有权
标题翻译：具有翅片的双极结晶体管
公开(公告)号：US08258602B2
公开(公告)日：2012-09-04
申请号：US12618425
申请日：2009-11-13
申请人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
发明人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/73 , H01L21/823431
摘要： Design and methods for fabricating bipolar junction transistors are described. In one embodiment, a semiconductor device includes a first fin comprising a first emitter region, a first base region, and a first collector region. The first emitter region, the first base region, and the first collector region form a bipolar junction transistor. A second fin is disposed adjacent and parallel to the first fin. The second fin includes a first contact to the first base region.
摘要翻译：描述用于制造双极结型晶体管的设计和方法。在一个实施例中，半导体器件包括包括第一发射极区域，第一基极区域和第一集电极区域的第一鳍片。第一发射极区域，第一基极区域和第一集电极区域形成双极结型晶体管。第二翅片邻近并平行于第一翅片设置。第二鳍片包括与第一基底区域的第一接触。

7. 发明授权

US08183910B2 Circuit and method for a digital process monitor 有权
标题翻译：数字过程监控的电路和方法
公开(公告)号：US08183910B2
公开(公告)日：2012-05-22
申请号：US12495024
申请日：2009-06-30
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L35/00 , H01L37/00 , H03K3/42 , H03K17/78
CPC分类号： G01R31/3004 , G01R31/31703
摘要： A circuit and method for a digital process monitor is disclosed. Circuits for comparing a current or voltage to a current or voltage corresponding to a device having process dependent circuit characteristics are disclosed, having converters for converting current or voltage measurements proportional to the process dependent circuit characteristic to a digital signal and outputting the digital signal for monitoring. The process dependent circuit characteristics may be selected from transistor threshold voltage, transistor saturation current, and temperature dependent quantities. Calibration is performed using digital techniques such as digital filtering and digital signal processing. The digital process monitor circuit may be formed as a scribe line circuit for wafer characterization or placed in an integrated circuit die as a macro. The process monitor circuit may be accessed using probe pads or scan test circuitry. Methods for monitoring process dependent characteristics using digital outputs are disclosed.
摘要翻译：公开了一种用于数字处理监视器的电路和方法。公开了用于将电流或电压与对应于具有过程相关电路特性的器件相对应的电流或电压进行比较的电路，具有用于将与过程相关的电路特性成比例的电流或电压测量值转换为数字信号的转换器，并输出用于监测的数字信号。处理相关电路特性可以选自晶体管阈值电压，晶体管饱和电流和温度依赖量。使用数字滤波和数字信号处理等数字技术进行校准。数字处理监视电路可以形成为用于晶片表征的划线电路或者作为宏放置在集成电路管芯中。可以使用探针焊盘或扫描测试电路来访问过程监控电路。公开了使用数字输出来监视与过程有关的特性的方法。

8. 发明授权

US07663445B2 Voltage-control oscillator circuits with combined MOS and bipolar device 有权
标题翻译：具有组合MOS和双极器件的压控振荡器电路
公开(公告)号：US07663445B2
公开(公告)日：2010-02-16
申请号：US12237187
申请日：2008-09-24
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1203 , H03B5/1212 , H03B5/1215 , H03B5/1231 , H03B5/124
摘要： A voltage controlled oscillator includes: a first merged device having a first bipolar transistor and a first MOS transistor, the first bipolar transistor having a collector sharing a common active area with a source/drain of the first MOS transistor, and an emitter sharing the common active area with another source/drain of the first MOS transistor, a second merged device having a second bipolar transistor and a second MOS transistor, the second bipolar transistor having a collector sharing a common active area with a source/drain of the second MOS transistor, and an emitter sharing the common active area with another source/drain of the second MOS transistor, and a first inductor connected to both the collector of the first bipolar transistor and a base of the second bipolar transistor.
摘要翻译：压控振荡器包括：具有第一双极晶体管和第一MOS晶体管的第一合并器件，所述第一双极晶体管具有与第一MOS晶体管的源极/漏极共用公共有效面积的集电极，以及共享公共具有第一MOS晶体管的另一源/漏极的有源区，具有第二双极晶体管和第二MOS晶体管的第二合并器件，所述第二双极晶体管具有与第二MOS晶体管的源极/漏极共用共用有效面积的集电极以及与第二MOS晶体管的另一个源极/漏极共用公共有源区域的发射极，以及连接到第一双极晶体管的集电极和第二双极晶体管的基极的第一电感器。

9. 发明授权

US07612638B2 Waveguides in integrated circuits 有权
标题翻译：集成电路中的波导
公开(公告)号：US07612638B2
公开(公告)日：2009-11-03
申请号：US11486903
申请日：2006-07-14
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H01P3/00 , H01P3/12 , H01P3/14 , H01P1/00 , H01P1/06
CPC分类号： H01P3/12 , H01L2924/0002 , H01L2924/00
摘要： A waveguide in semiconductor integrated circuit is disclosed, the waveguide comprises a horizontal first metal plate, a horizontal second metal plate above the first metal plate, separated by an insulation material, and a plurality of metal vias positioned in two parallel lines, running vertically through the insulation material in contacts with both the first and second metal plates, wherein the first and second metal plates and the plurality of metal vias form a metal enclosure in a cross-sectional view that can serve as a waveguide.
摘要翻译：公开了一种半导体集成电路中的波导，波导包括水平的第一金属板，在第一金属板上方的水平的第二金属板，由绝缘材料隔开，并且多个金属通孔位于两条平行的线上，垂直延伸穿过所述绝缘材料与所述第一和第二金属板两者接触，其中所述第一和第二金属板和所述多个金属通孔以横截面视图形成可用作波导的金属外壳。

10. 发明申请

US20090002058A1 Automatic Bias Circuit for Sense Amplifier 有权
标题翻译：用于检测放大器的自动偏置电路
公开(公告)号：US20090002058A1
公开(公告)日：2009-01-01
申请号：US11769611
申请日：2007-06-27
申请人： Po Yao Ker , Shine Chung , Fu-Lung Hsueh
发明人： Po Yao Ker , Shine Chung , Fu-Lung Hsueh
IPC分类号： H01H37/76 , G11C5/14
CPC分类号： G11C17/18 , G11C5/147
摘要： The present invention discloses a bias circuit for a sense amplifier having a device under sensing, the device under sensing having an un-programmed state and a programmed state, the bias circuit comprises at least one first branch having at least one first device formed substantially the same as the device under sensing and remaining in the un-programmed state, and at least one second device formed also substantially the same as the device under sensing and being in the programmed state, wherein the at least one first device and the at least one second device are serially connected. A typical application of the present invention is an electrical fuse memory.
摘要翻译：本发明公开了一种用于感测放大器的偏置电路，其具有被感测的器件，该感测器件处于非编程状态和编程状态，该偏置电路包括至少一个第一分支，该第一分支具有至少一个基本上形成与感测下的设备相同并且保持在未编程状态，并且至少一个第二设备形成也与感测下的设备基本相同并处于编程状态，其中至少一个第一设备和至少一个第二设备串联连接。本发明的典型应用是电熔丝存储器。

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