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1. 发明授权

US6037807A Synchronous sense amplifier with temperature and voltage compensated translator 失效
标题翻译：具有温度和电压补偿转换器的同步读出放大器
公开(公告)号：US6037807A
公开(公告)日：2000-03-14
申请号：US80710
申请日：1998-05-18
申请人： Chau-Chin Wu , Ta-Ke Tien , Wen-Kuan Fang
发明人： Chau-Chin Wu , Ta-Ke Tien , Wen-Kuan Fang
IPC分类号： G11C7/06 , H01L35/00
CPC分类号： G11C7/06
摘要： A bias control circuit for controlling the bias current in a sense amplifier circuit. The bias control circuit maintains a substantially constant bias current when the V.sub.CC supply voltage decreases, thereby maintaining the operating speed of the sense amplifier circuit at a predetermined level. The bias control circuit also increases the bias current as the temperature of the sense amplifier circuit increases, thereby maintaining the operating speed of the sense amplifier circuit at the predetermined level. Furthermore, the bias circuit controls the logic low voltage provided by the sense amplifier circuit to be less than a predetermined threshold value, even as the V.sub.CC supply voltage increases.
摘要翻译：用于控制读出放大器电路中的偏置电流的偏置控制电路。当VCC电源电压降低时，偏置控制电路保持基本恒定的偏置电流，从而将读出放大器电路的工作速度保持在预定的水平。当感测放大器电路的温度升高时，偏置控制电路也增加偏置电流，从而将读出放大器电路的工作速度保持在预定的水平。此外，即使VCC电源电压增加，偏置电路将由读出放大器电路提供的逻辑低电压控制为小于预定阈值。

2. 发明授权

US5994945A Circuit for compensating for variations in both temperature and supply voltage 失效
标题翻译：用于补偿温度和电源电压变化的电路
公开(公告)号：US5994945A
公开(公告)日：1999-11-30
申请号：US40329
申请日：1998-03-16
申请人： Chau-Chin Wu , Ta-Ke Tien , Kuo-Huei Yen
发明人： Chau-Chin Wu , Ta-Ke Tien , Kuo-Huei Yen
IPC分类号： H03K19/003 , H03K17/14
CPC分类号： H03K19/00384
摘要： A compensation circuit which accounts for variations in both temperature and V.sub.CC supply voltage on an integrated circuit. The compensation circuit includes four quasi-independent compensation current sources, each of which generates a corresponding compensation current. The first compensation current source generates a first compensation current which has a positive slope with respect to temperature. The second compensation current source generates a second compensation current which has a negative slope with respect to temperature. The third compensation current source generates a third compensation current which has a negative slope with respect to the V.sub.CC supply voltage. The fourth compensation current source generates a fourth compensation current which has a positive slope with respect to the V.sub.CC supply voltage. The first, second, third and fourth compensation currents are summed to create a total compensation current. The compensation current sources are designed to provide different, pre-determined total compensation currents for different temperatures and supply voltages. The predetermined total compensation currents are selected to cause the compensated circuit to transfer signals at a constant speed, regardless of temperature and supply voltage.
摘要翻译：考虑到集成电路的温度和VCC电源电压变化的补偿电路。补偿电路包括四个准独立的补偿电流源，每个补偿电流源产生相应的补偿电流。第一补偿电流源产生相对于温度具有正斜率的第一补偿电流。第二补偿电流源产生相对于温度具有负斜率的第二补偿电流。第三补偿电流源产生相对于VCC电源电压具有负斜率的第三补偿电流。第四补偿电流源产生相对于VCC电源电压具有正斜率的第四补偿电流。将第一，第二，第三和第四补偿电流相加以产生总补偿电流。补偿电流源设计为不同的温度和电源电压提供不同的预定总补偿电流。选择预定的总补偿电流以使补偿电路以恒定速度传送信号，而不管温度和电源电压如何。

3. 发明授权

US5517131A TTL input buffer with on-chip reference bias regulator and decoupling capacitor 失效
标题翻译：具有片内基准偏置调节器和去耦电容的TTL输入缓冲器
公开(公告)号：US5517131A
公开(公告)日：1996-05-14
申请号：US295322
申请日：1994-08-23
申请人： Ta-Ke Tien , Chau-chin Wu , Richard C. Li
发明人： Ta-Ke Tien , Chau-chin Wu , Richard C. Li
IPC分类号： H03K19/003 , H03K19/0185 , H03K17/16
CPC分类号： H03K19/00384 , H03K19/018521
摘要： An input buffer insensitive to changes in supply voltage, temperature and other operational parameters comprises a decoupling capacitor and receives a reference voltage. In one embodiment, the input buffer comprises a CMOS invertor in which a PMOS transistor is provided to decouple the output signal from a fluctuation of the ground voltage ("ground bounce"). In one embodiment, a band gap type voltage regulator provides the reference voltage of the input buffer.
摘要翻译：对电源电压，温度和其他操作参数变化不敏感的输入缓冲器包括去耦电容并接收参考电压。在一个实施例中，输入缓冲器包括CMOS反相器，其中提供PMOS晶体管以将输出信号与接地电压（“接地反弹”）的波动分离。在一个实施例中，带隙型电压调节器提供输入缓冲器的参考电压。

4. 发明授权

US06388499B1 Level-shifting signal buffers that support higher voltage power supplies using lower voltage MOS technology 失效
标题翻译：电平移位信号缓冲器，支持使用较低电压MOS技术的高压电源
公开(公告)号：US06388499B1
公开(公告)日：2002-05-14
申请号：US09770099
申请日：2001-01-25
申请人： Ta-Ke Tien , Chau-Chin Wu
发明人： Ta-Ke Tien , Chau-Chin Wu
IPC分类号： H03K190185
CPC分类号： H03K19/00315
摘要： A level-shifting signal buffer contains a totem pole arrangement of MOS transistors connected to an output thereof and a control circuit that drives the totem pole arrangement of MOS transistors in a preferred manner so that none of the signals across the MOS transistors exceed predetermined limits that may damage the MOS transistors. A preferred signal buffer may include a PMOS pull-up transistor and an NMOS pull-down transistor arranged within a transistor totem pole. This transistor totem pole extends between a first power supply signal line that receives a first power supply signal (e.g., Vddext) and a reference signal line that receives a reference signal (e.g., GND). The PMOS pull-up transistor may be configured to support a maximum gate-to-drain voltage which is less than a difference in voltage between the first power supply signal and the reference signal. The control circuit, which is responsive to a data input signal, drives gate electrodes of the PMOS pull-up transistor and the NMOS pull-down transistor with signals that cause an output of the transistor totem pole to swing from a voltage of the first power supply signal line to a voltage of the reference signal line during a pull-down time interval, while simultaneously maintaining a gate-to-drain voltage of the PMOS pull-down transistor within the maximum gate-to-drain voltage throughout the pull-down time interval.
摘要翻译：电平移位信号缓冲器包含连接到其输出的MOS晶体管的图腾柱布置，以及以优选方式驱动MOS晶体管的图腾柱布置的控制电路，使得MOS晶体管两端的信号都不超过预定的限制，可能会损坏MOS晶体管。优选的信号缓冲器可以包括布置在晶体管图腾柱内的PMOS上拉晶体管和NMOS下拉晶体管。该晶体管图腾柱在接收第一电源信号（例如，Vddext）的第一电源信号线和接收参考信号（例如，GND）的参考信号线之间延伸。 PMOS上拉晶体管可以被配置为支持小于第一电源信号和参考信号之间的电压差的最大栅极 - 漏极电压。响应于数据输入信号的控制电路利用引起晶体管图腾柱的输出从第一功率的电压摆动的信号驱动PMOS上拉晶体管和NMOS下拉晶体管的栅极电极在下拉时间间隔期间将信号线提供给参考信号线的电压，同时在下拉时同时将PMOS下拉晶体管的栅极至漏极电压保持在最大栅极至漏极电压内时间间隔。

5. 发明授权

US06421265B1 DRAM-based CAM cell using 3T or 4T DRAM cells 有权
标题翻译：基于DRAM的CAM单元使用3T或4T DRAM单元
公开(公告)号：US06421265B1
公开(公告)日：2002-07-16
申请号：US09816742
申请日：2001-03-22
申请人： Chuen-Der Lien , Chau-Chin Wu , Ta-Ke Tien
发明人： Chuen-Der Lien , Chau-Chin Wu , Ta-Ke Tien
IPC分类号： G11C1500
CPC分类号： G11C15/043 , G11C15/04
摘要： A CAM cell including three-transistor (3T) or four-transistor (4T) DRAM cells. Data is stored using intrinsic capacitance of each 3T or 4T DRAM cell, and is applied to the gate terminal of a pull-down transistor. Read operations are performed in the 3T and 4T DRAM cells without disturbing the stored data value by applying the stored data value to the gate terminal of a pull-down transistor and detecting the operating state (i.e., turned on or turned off) of a pull-down transistor, thereby avoiding the charge sharing problems associated with 1T DRAM cells.
摘要翻译：包括三晶体管（3T）或四晶体管（4T）DRAM单元的CAM单元。使用每个3T或4T DRAM单元的固有电容来存储数据，并且被施加到下拉晶体管的栅极端子。通过将存储的数据值应用于下拉晶体管的栅极端子并检测拉动的操作状态（即，导通或关闭），在3T和4T DRAM单元中执行读操作，而不会干扰存储的数据值降低晶体管，从而避免与1T DRAM单元相关的电荷共享问题。

6. 发明授权

US5376843A TTL input buffer with on-chip reference bias regulator and decoupling capacitor 失效
标题翻译：具有片内基准偏置调节器和去耦电容的TTL输入缓冲器
公开(公告)号：US5376843A
公开(公告)日：1994-12-27
申请号：US929872
申请日：1992-08-11
申请人： Ta-Ke Tien , Chau-chin Wu , Richard C. Li
发明人： Ta-Ke Tien , Chau-chin Wu , Richard C. Li
IPC分类号： H03K19/003 , H03K19/0185 , H03K19/20
CPC分类号： H03K19/00384 , H03K19/018521
摘要： An input buffer insensitive to changes in supply voltage, temperature and other operational parameters comprises a decoupling capacitor and receives a reference voltage. In one embodiment, the input buffer comprises a CMOS invertor in which a PMOS transistor is provided to decouple the output signal from a fluctuation of the ground voltage ("ground bounce"). In one embodiment, a band gap type voltage regulator provides the reference voltage of the input buffer.
摘要翻译：对电源电压，温度和其他操作参数变化不敏感的输入缓冲器包括去耦电容并接收参考电压。在一个实施例中，输入缓冲器包括CMOS反相器，其中提供PMOS晶体管以将输出信号与接地电压（“接地反弹”）的波动分离。在一个实施例中，带隙型电压调节器提供输入缓冲器的参考电压。

7. 发明授权

US06724601B2 ESD protection circuit 有权
标题翻译： ESD保护电路
公开(公告)号：US06724601B2
公开(公告)日：2004-04-20
申请号：US09811114
申请日：2001-03-16
申请人： Chuen-Der Lien , Chau-Chin Wu , Ta-Ke Tien
发明人： Chuen-Der Lien , Chau-Chin Wu , Ta-Ke Tien
IPC分类号： H02H900
CPC分类号： H01L27/0251
摘要： An integrated circuit having an electrostatic discharge (ESD) protection circuit, a core protection circuit, a sensitive core circuit and peripheral circuitry is provided. The ESD protection circuit is coupled between the VDD voltage supply terminal and the VSS voltage supply terminal, and is capable of providing protection to the peripheral circuitry. The ESD protection circuitry requires help from core protection circuit to protect the sensitive core circuit. The core protection circuit and the sensitive core circuit are coupled in series between the VDD and VSS voltage supply terminals, with the core protection circuit coupled to the VDD voltage supply terminal. The sensitive core circuit has a VCC voltage supply terminal coupled to receive a VCC supply voltage from the core protection circuit. The core protection circuit is configured to cause the VCC supply voltage to rise slowly with respect to a rising voltage on the VDD voltage supply terminal during power-on of the integrated circuit. The core protection circuit is further configured to disconnect the VCC voltage supply terminal from the VDD voltage supply when a voltage on the VDD voltage supply terminal exceeds the nominal VDD supply voltage by a predetermined amount.
摘要翻译：提供具有静电放电（ESD）保护电路，核心保护电路，敏感核心电路和外围电路的集成电路。 ESD保护电路耦合在VDD电压端子和VSS电压端子之间，能够为外围电路提供保护。 ESD保护电路需要核心保护电路的帮助来保护敏感的核心电路。核心保护电路和敏感核心电路串联在VDD和VSS电压端子之间，核心保护电路耦合到VDD电源端。敏感核心电路具有VCC电压供应端，耦合以从核心保护电路接收VCC电源电压。核心保护电路被配置为使得在电源上的VCC电源电压相对于VDD电压端上升的电压缓慢上升。核心保护电路还被配置为当VDD电压端子上的电压超过标称VDD电源电压预定量时，将VCC电压源端子与VDD电压源断开。

8. 发明授权

US5483183A Bipolar current sense amplifier 失效
标题翻译：双极电流检测放大器
公开(公告)号：US5483183A
公开(公告)日：1996-01-09
申请号：US194773
申请日：1994-02-10
申请人： Richard C. Li , Chau-Chin Wu , Ta-Ke Tien
发明人： Richard C. Li , Chau-Chin Wu , Ta-Ke Tien
IPC分类号： H03F3/45 , H03K5/24 , G01R19/00
CPC分类号： H03F3/45085 , H03K5/2418 , H03F2203/45352 , H03F2203/45374 , H03F2203/45544 , H03F2203/45564 , H03F2203/45654 , H03F2203/45702
摘要： In a sense amplifier, collectors of a first pair of transistors are connected to and drive the bases of a pair of output transistors, and the bases of the first pair of transistors and the emitters of the pair of output transistors are coupled to input nodes of the sense amplifier. The speed of the sense amplifier is enhanced over the prior art because changes in currents (or voltages) on the input nodes change both the emitter and base voltages of the pair of output transistors.
摘要翻译：在读出放大器中，第一对晶体管的集电极连接到一对输出晶体管的基极并驱动一对输出晶体管的基极，并且第一对晶体管的基极和一对输出晶体管的发射极耦合到读出放大器。由于输入节点上的电流（或电压）的变化改变了一对输出晶体管的发射极和基极电压，所以读出放大器的速度比现有技术增强。

9. 发明授权

US5341333A Circuits and methods for amplification of electrical signals 失效
标题翻译：电信号放大的电路和方法
公开(公告)号：US5341333A
公开(公告)日：1994-08-23
申请号：US929874
申请日：1992-08-11
申请人： Ta-Ke Tien , Chau-Chin Wu
发明人： Ta-Ke Tien , Chau-Chin Wu
IPC分类号： G11C7/06
CPC分类号： G11C7/062
摘要： An amplifier used in some embodiments as a sense amplifier for a memory includes a plurality of first sense amplifiers 220.i whose outputs are connected to high capacitance nodes SA, SA which in turn are connected to inputs of second sense amplifier 240. The state of nodes SA, SA is defined by the currents on the two nodes. The voltages on nodes SA, SA, however, are kept substantially constant, which increases the state switching speed and reduces the power consumption. When the amplifier is not in use and the power-down circuitry reconfigures the amplifier to reduce the power consumption, the second amplifier 240 places its output OUT2 into a valid state in order to prevent oscillations of the output and to reduce power consumption. When the amplifier returns from the power-down mode, the output OUT2 is kept in that state until nodes SA, SA and certain other nodes within the first and second amplifiers settle to proper current and voltage values. As a result, during settling the oscillations on output OUT are prevented and power consumption is reduced.
摘要翻译：在一些实施例中用作存储器的读出放大器的放大器包括多个第一读出放大器220.i，其输出端连接到高电容节点SA，并且上和下连接到第二读出放大器240的输入端。状态节点SA，＆upbar＆S由两个节点上的电流定义。然而，节点SA，＆upbar＆S上的电压保持基本恒定，这增加了状态切换速度并降低了功耗。当放大器未被使用并且掉电电路重新配置放大器以降低功耗时，第二放大器240将其输出OUT2置于有效状态，以便防止输出的振荡并降低功耗。当放大器从掉电模式返回时，输出OUT2保持在该状态，直到第一和第二放大器中的节点SA，上升沿S和某些其他节点达到适当的电流和电压值。结果，在稳定期间，防止输出OUT上的振荡并降低功耗。

10. 发明授权

US07522395B1 Electrostatic discharge and electrical overstress protection circuit 失效
标题翻译：静电放电和电气过载保护电路
公开(公告)号：US07522395B1
公开(公告)日：2009-04-21
申请号：US11063703
申请日：2005-02-22
申请人： Ta-Ke Tien , Tar Hear Maung
发明人： Ta-Ke Tien , Tar Hear Maung
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： Electrostatic discharge and electrical overstress protection circuit is disclosed to include a discharging circuit, a detection circuit and a controller. The controller is operable to sense and compare the output voltage from the detection circuit to a reference voltage. The controller, upon detection of a normal operating condition or an electrical overstress (EOS) situation, is operable to cause the discharging circuit to discharge any excess voltage from the voltage supply to the electrical ground at a safety voltage level. The controller, upon detection of an electrostatic discharge (ESD) event, is operable to cause the discharging circuit to discharge the excess voltage at a second voltage level that is less than the safety voltage level.
摘要翻译：公开了静电放电和电过载保护电路，包括放电电路，检测电路和控制器。控制器可操作以感测和比较来自检测电路的输出电压与参考电压。控制器在检测到正常操作条件或电应力（EOS）情况时，可操作地使得放电电路在任何安全电压电平下将任何过剩电压从电压源放电到电接地。控制器在检测到静电放电（ESD）事件时可操作地使放电电路以小于安全电压电平的第二电压电平放电过剩电压。

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