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1. 发明授权

US09397729B2 Through chip coupling for signal transport 有权
标题翻译：通过芯片耦合进行信号传输
公开(公告)号：US09397729B2
公开(公告)日：2016-07-19
申请号：US12946072
申请日：2010-11-15
申请人： Tzu-Jin Yeh , Hsieh-Hung Hsieh , Jun-De Jin , Ming Hsien Tsai , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： Tzu-Jin Yeh , Hsieh-Hung Hsieh , Jun-De Jin , Ming Hsien Tsai , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H04B5/00
CPC分类号： H04B5/0081
摘要： Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit.
摘要翻译：芯片耦合用于信号传输，其中在第一集成电路（IC）芯片上的第一线圈和第二IC芯片上的第二线圈之间形成接口。第一线圈耦合到天线。第二线圈耦合到放大器电路。第二线圈不与第一线圈直接接触。第一线圈和第二线圈在天线和第一放大器电路之间通信地传送信号。

2. 发明授权

US09165968B2 3D-stacked backside illuminated image sensor and method of making the same 有权
标题翻译： 3D叠层背面照明图像传感器及其制作方法
公开(公告)号：US09165968B2
公开(公告)日：2015-10-20
申请号：US13616850
申请日：2012-09-14
申请人： Calvin Yi-Ping Chao , Kuo-Yu Chou , Fu-Lung Hsueh
发明人： Calvin Yi-Ping Chao , Kuo-Yu Chou , Fu-Lung Hsueh
IPC分类号： H01L27/146 , H04N5/374
CPC分类号： H01L27/14634 , H01L27/14636 , H01L27/1464 , H01L27/14641 , H04N5/374
摘要： A stacked image sensor and method for making the same are provided. The stacked image sensor includes an upper chip with a pixel array thereon. The second chip includes a plurality of column circuits and row circuits associated with the columns and rows of the pixel array and disposed in respective column circuit and row circuit regions that are arranged in multiple groups. Inter-chip bonding pads are formed on each of the chips. The inter-chip bonding pads on the second chip are arranged linearly and are contained within the column circuit regions and row circuit regions in one embodiment. In other embodiments, the inter-chip bonding pads are staggered with respect to each other. In some embodiments, the rows and columns of the pixel array include multiple signal lines and the corresponding column circuit regions and row circuit regions also include multiple inter-chip bonding pads.
摘要翻译：提供一种堆叠式图像传感器及其制造方法。堆叠图像传感器包括其上具有像素阵列的上部芯片。第二芯片包括与像素阵列的列和行相关联的多个列电路和行电路，并且被布置在多个组中的各个列电路和行电路区域中。在每个芯片上形成芯片间接合焊盘。在一个实施例中，第二芯片上的芯片间接合焊盘被线性布置并且被包含在列电路区域和行电路区域内。在其他实施例中，芯片间接合焊盘相对于彼此交错。在一些实施例中，像素阵列的行和列包括多个信号线，并且相应的列电路区域和行电路区域还包括多个芯片间接合焊盘。

3. 发明授权

US08890626B2 Divider-less phase locked loop (PLL) 有权
标题翻译：无分频锁相环（PLL）
公开(公告)号：US08890626B2
公开(公告)日：2014-11-18
申请号：US13586033
申请日：2012-08-15
申请人： Yen-Jen Chen , I-Ting Lee , Hsieh-Hung Hsieh , Chewn-Pu Jou , Fu-Lung Hsueh , Shen-Iuan Liu
发明人： Yen-Jen Chen , I-Ting Lee , Hsieh-Hung Hsieh , Chewn-Pu Jou , Fu-Lung Hsueh , Shen-Iuan Liu
IPC分类号： H03K3/03
CPC分类号： H03K3/0322 , H03K3/0315 , H03L7/083 , H03L7/087 , H03L7/089 , H03L7/099
摘要： One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.
摘要翻译：本文提供了一种用于无分频锁相环（PLL）和相关相位检测器（PD）的技术和系统。在一些实施例中，接收脉冲相位检测器（pulsePD）信号，压控振荡器正差分（VCOP）信号和压控振荡器负差分（VCON）信号。基于pulsePD信号，VCOP信号和VCON信号产生用于第一电荷泵（CP）的上升信号和下降信号以及用于第二CP的上升信号和下降信号。例如，生成CP信号以分别控制第一CP和第二CP。在一些实施例中，产生CP信号，使得CP有助于调整相对于pulsePD信号的VCON和VCOP信号的零交叉相位。以这种方式，提供无分频PLL，从而减轻PLL功耗。

4. 发明授权

US08847321B2 Cascode CMOS structure 有权
标题翻译： Cascode CMOS结构
公开(公告)号：US08847321B2
公开(公告)日：2014-09-30
申请号：US12766972
申请日：2010-04-26
申请人： Fu-Lung Hsueh , Chih-Ping Chao , Chewn-Pu Jou , Yung-Chow Peng , Harry-Hak-Lay Chuang , Kuo-Tung Sung
发明人： Fu-Lung Hsueh , Chih-Ping Chao , Chewn-Pu Jou , Yung-Chow Peng , Harry-Hak-Lay Chuang , Kuo-Tung Sung
IPC分类号： H01L29/78 , G06F17/50 , H01L27/088
CPC分类号： G06F17/5068 , G06F17/50 , G06F17/5009 , H01L27/088 , H01L27/0922
摘要： A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.
摘要翻译： MOS器件包括具有第一和第二触点的有源区。第一和第二栅极设置在第一和第二触点之间。第一门被设置成与第一接触相邻并且具有第三接触。第二栅极被设置成与第二触点相邻并且具有耦合到第三触点的第四触点。由有源区和第一栅极限定的晶体管具有第一阈值电压，并且由有源区和第二栅极限定的晶体管具有第二阈值电压。

5. 发明授权

US08729968B2 Built-in self-test circuit for voltage controlled oscillators 有权
标题翻译：用于压控振荡器的内置自检电路
公开(公告)号：US08729968B2
公开(公告)日：2014-05-20
申请号：US13103571
申请日：2011-05-09
申请人： Hsieh-Hung Hsieh , Ming Hsien Tsai , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
发明人： Hsieh-Hung Hsieh , Ming Hsien Tsai , Tzu-Jin Yeh , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H03L5/00
CPC分类号： G01R31/2824
摘要： A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.
摘要翻译：用于测试压控振荡器的内置自检电路包括压控振荡器，具有耦合到压控振荡器的输出的输入的缓冲器和耦合到缓冲器的输出的射频峰值检测器。射频峰值检测器被配置为从压控振荡器接收交流信号，并且在射频峰值检测器的输出处产生与ac信号成比例的直流值。此外，当压控振荡器正常工作时，射频峰值检测器的输出产生与来自压控振荡器的ac信号的幅度成比例的直流值。另一方面，当压控振荡器不能产生交流信号时，射频峰值检测器的输出为零伏特。

6. 发明申请

US20140077057A1 3D-STACKED BACKSIDE ILLUMINATED IMAGE SENSOR AND METHOD OF MAKING THE SAME 有权
标题翻译： 3D堆叠式背光照明图像传感器及其制作方法
公开(公告)号：US20140077057A1
公开(公告)日：2014-03-20
申请号：US13616850
申请日：2012-09-14
申请人： Calvin Yi-Ping CHAO , Kuo-Yu CHOU , Fu-Lung HSUEH
发明人： Calvin Yi-Ping CHAO , Kuo-Yu CHOU , Fu-Lung HSUEH
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14634 , H01L27/14636 , H01L27/1464 , H01L27/14641 , H04N5/374
摘要： A stacked image sensor and method for making the same are provided. The stacked image sensor includes an upper chip with a pixel array thereon. The second chip includes a plurality of column circuits and row circuits associated with the columns and rows of the pixel array and disposed in respective column circuit and row circuit regions that are arranged in multiple groups. Inter-chip bonding pads are formed on each of the chips. The inter-chip bonding pads on the second chip are arranged linearly and are contained within the column circuit regions and row circuit regions in one embodiment. In other embodiments, the inter-chip bonding pads are staggered with respect to each other. In some embodiments, the rows and columns of the pixel array include multiple signal lines and the corresponding column circuit regions and row circuit regions also include multiple inter-chip bonding pads.
摘要翻译：提供一种堆叠式图像传感器及其制造方法。堆叠图像传感器包括其上具有像素阵列的上部芯片。第二芯片包括与像素阵列的列和行相关联的多个列电路和行电路，并且被布置在多个组中的各个列电路和行电路区域中。在每个芯片上形成芯片间接合焊盘。在一个实施例中，第二芯片上的芯片间接合焊盘被线性布置并且被包含在列电路区域和行电路区域内。在其他实施例中，芯片间接合焊盘相对于彼此交错。在一些实施例中，像素阵列的行和列包括多个信号线，并且相应的列电路区域和行电路区域还包括多个芯片间接合焊盘。

7. 发明授权

US08588358B2 Clock and data recovery using LC voltage controlled oscillator and delay locked loop 有权
标题翻译：使用LC压控振荡器和延迟锁定环的时钟和数据恢复
公开(公告)号：US08588358B2
公开(公告)日：2013-11-19
申请号：US13045788
申请日：2011-03-11
申请人： Chan-Hong Chern , Chih-Chang Lin , Ming-Chieh Huang , Fu-Lung Hsueh
发明人： Chan-Hong Chern , Chih-Chang Lin , Ming-Chieh Huang , Fu-Lung Hsueh
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/081 , H03L7/113 , H04L7/0337
摘要： A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases.
摘要翻译：时钟和数据恢复（CDR）电路包括被配置为产生具有时钟频率的时钟信号的电感器 - 电容器压控振荡器（LCVCO）。延迟锁定环（DLL）被配置为从LCVCO接收时钟信号并生成多个时钟相位。电荷泵配置为控制LCVCO。相位检测器被配置为从DLL接收数据输入和多个时钟相位，并且控制第一电荷泵以便对准数据输入和多个时钟相位的数据沿。

8. 发明申请

US20130241634A1 RF CALIBRATION THROUGH-CHIP INDUCTIVE COUPLING 有权
标题翻译： RF校准通过芯片感应耦合
公开(公告)号：US20130241634A1
公开(公告)日：2013-09-19
申请号：US13419911
申请日：2012-03-14
申请人： Hsieh-Hung HSIEH , Yi-Hsuan LIU , Tzu-Jin YEH , Chewn-Pu JOU , Fu-Lung HSUEH
发明人： Hsieh-Hung HSIEH , Yi-Hsuan LIU , Tzu-Jin YEH , Chewn-Pu JOU , Fu-Lung HSUEH
IPC分类号： H01L25/00
CPC分类号： H01L23/48 , H01L23/66 , H01L25/0657 , H01L2225/06531 , H01L2924/0002 , H04B5/0075 , H01L2924/00
摘要： An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils.
摘要翻译：集成电路包括在垂直堆叠中耦合到第一芯片的第一芯片和第二芯片。第一芯片包括射频电路和电耦合到射频电路的第一线圈。第二芯片包括校准电路和电耦合到校准电路的第二线圈。校准电路被配置为通过第一和第二线圈之间的感应耦合来校准设置在第一芯片上的射频电路。

9. 发明授权

US08493124B2 Low minimum power supply voltage level shifter 有权
标题翻译：低最小电源电压电平转换器
公开(公告)号：US08493124B2
公开(公告)日：2013-07-23
申请号：US12843479
申请日：2010-07-26
申请人： Chan-Hong Chern , Fu-Lung Hsueh , Ming-Chieh Huang , Chih-Chang Lin
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Ming-Chieh Huang , Chih-Chang Lin
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A level shifter includes one PMOS and two NMOS transistors. A source of the first NMOS transistor is coupled to a low power supply voltage. An input signal is coupled to a gate of the first NMOS transistor and a source of the second NMOS transistor. The input signal has a voltage level up to a first power supply voltage. A source of the PMOS transistor is coupled to a second power supply voltage, higher than the first power supply voltage. An output signal is coupled between the PMOS and the first NMOS transistors. The first NMOS transistor is arranged to pull down the output signal when the input signal is a logical 1, and the second NMOS transistor is arranged to enable the PMOS transistor to pull up the output signal to a logical 1 at the second power supply voltage when the input signal is a logical 0.
摘要翻译：电平移位器包括一个PMOS和两个NMOS晶体管。第一NMOS晶体管的源极耦合到低电源电压。输入信号耦合到第一NMOS晶体管的栅极和第二NMOS晶体管的源极。输入信号具有高达第一电源电压的电压电平。 PMOS晶体管的源极耦合到高于第一电源电压的第二电源电压。输出信号耦合在PMOS和第一NMOS晶体管之间。第一NMOS晶体管被布置为当输入信号为逻辑1时下拉输出信号，并且第二NMOS晶体管被布置为使得PMOS晶体管能够以第二电源电压将输出信号上拉至逻辑1，输入信号为逻辑0。

10. 发明授权

US08436671B2 Level shifters having diode-connected devices for input-output interfaces 有权
标题翻译：电平移位器具有用于输入 - 输出接口的二极管连接器件
公开(公告)号：US08436671B2
公开(公告)日：2013-05-07
申请号：US12859456
申请日：2010-08-19
申请人： Chan-Hong Chern , Fu-Lung Hsueh , Chih-Chang Lin , Yuwen Swei , Ming-Chieh Huang
发明人： Chan-Hong Chern , Fu-Lung Hsueh , Chih-Chang Lin , Yuwen Swei , Ming-Chieh Huang
IPC分类号： H03L5/00
CPC分类号： H03K3/02 , H03K19/018521 , H03K19/018528
摘要： A level shifter includes an input node, an output node, a pull-up transistor, a pull-down transistor, and at least one diode-connected device coupled between the pull-up transistor and the pull-down transistor. The level shifter is arranged to be coupled to a high power supply voltage, to receive an input signal having a first voltage level at the input node, and to supply an output signal having a second voltage level at the output node. The high power supply voltage is higher than the first voltage level. The at least one diode-connected device allows the output signal to be pulled up to about a first diode voltage drop below the high power supply voltage and/or to be pulled down to about a second diode voltage drop above ground. The first diode voltage drop and the second diode voltage drop are from the at least one diode-connected device.
摘要翻译：电平移位器包括输入节点，输出节点，上拉晶体管，下拉晶体管以及耦合在上拉晶体管和下拉晶体管之间的至少一个二极管连接器件。电平移位器被布置为耦合到高电源电压，以在输入节点处接收具有第一电压电平的输入信号，并且在输出节点处提供具有第二电压电平的输出信号。高电源电压高于第一电压电平。所述至少一个二极管连接的装置允许输出信号被上拉到大约低于高电源电压的第一二极管电压降和/或被下拉到大约地面上的第二二极管电压降。第一二极管电压降和第二二极管压降来自至少一个二极管连接的器件。

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