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1. 发明授权

US08202810B2 Low-H plasma treatment with N2 anneal for electronic memory devices 有权
标题翻译：用于电子存储器件的N 2退火的低-H等离子体处理
公开(公告)号：US08202810B2
公开(公告)日：2012-06-19
申请号：US11971331
申请日：2008-01-09
申请人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Erik Wilson , Sung Jin Kim , Hieu Trung Pham
发明人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Erik Wilson , Sung Jin Kim , Hieu Trung Pham
IPC分类号： H01L21/31
CPC分类号： H01L21/76877 , H01L21/76814 , H01L21/76828 , H01L21/76834 , H01L21/76883 , Y10S438/902
摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.
摘要翻译：一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

2. 发明授权

US06514865B1 Method of reducing interlayer dielectric thickness variation feeding into a planarization process 失效
标题翻译：将层间电介质厚度变化减小到平坦化过程的方法
公开(公告)号：US06514865B1
公开(公告)日：2003-02-04
申请号：US10044532
申请日：2002-01-11
申请人： Allen L. Evans
发明人： Allen L. Evans
IPC分类号： H01L21302
CPC分类号： H01L22/20
摘要： A method is provided that comprises forming a first dielectric layer on a workpiece, measuring a thickness of the first dielectric layer, and forming a second dielectric layer above the first dielectric layer, the second dielectric layer being formed to a thickness that is determined based upon the measured thickness of the first dielectric layer.
摘要翻译：提供了一种方法，其包括在工件上形成第一电介质层，测量第一电介质层的厚度，以及在第一电介质层之上形成第二电介质层，第二电介质层形成为基于测量第一介电层的厚度。

3. 发明授权

US06512991B1 Method and apparatus for reducing deposition variation by modeling post-clean chamber performance 有权
标题翻译：通过建模后清洁室性能来减少沉积变化的方法和装置
公开(公告)号：US06512991B1
公开(公告)日：2003-01-28
申请号：US09614312
申请日：2000-07-12
申请人： Bradley M. Davis , Allen L. Evans , Craig W. Christian
发明人： Bradley M. Davis , Allen L. Evans , Craig W. Christian
IPC分类号： G01K120
CPC分类号： G01K7/42
摘要： A method for reducing deposition thickness variation in a processing tool comprises storing a post-clean performance model of the processing tool; receiving at least one of a showerhead age and a tool idle time associated with the processing tool as an input parameter; determining temperature control parameters based on the input parameter and the post-clean performance model; and modifying an operating recipe of the processing tool based on the temperature control parameters. A processing system includes a processing tool and an automatic process controller. The processing tool is adapted to process wafers in accordance with an operating recipe. The automatic process controller is adapted to store a post-clean performance model of the processing tool, receive at least one of a showerhead age and a tool idle time associated with the processing tool as an input parameter, determine temperature control parameters based on the input parameter and the post-clean performance model, and modify the operating recipe of the processing tool based on the temperature control parameters.
摘要翻译：一种用于减少处理工具中的沉积厚度变化的方法包括：存储处理工具的后清洁性能模型; 接收与处理工具相关联的喷头年龄和工具空闲时间中的至少一个作为输入参数; 根据输入参数和清洁后性能模型确定温度控制参数; 以及基于所述温度控制参数来修改所述处理工具的操作配方。处理系统包括处理工具和自动过程控制器。处理工具适于根据操作配方处理晶片。自动过程控制器适于存储处理工具的后清洁性能模型，接收与处理工具相关联的喷头年龄和工具空闲时间中的至少一个作为输入参数，基于输入来确定温度控制参数参数和清洁后性能模型，并根据温度控制参数修改加工工具的操作配方。

4. 发明授权

US06469518B1 Method and apparatus for determining measurement frequency based on hardware age and usage 有权
标题翻译：基于硬件年龄和使用情况确定测量频率的方法和装置
公开(公告)号：US06469518B1
公开(公告)日：2002-10-22
申请号：US09479180
申请日：2000-01-07
申请人： Bradley M. Davis , Allen L. Evans , Craig W. Christian
发明人： Bradley M. Davis , Allen L. Evans , Craig W. Christian
IPC分类号： G01R2700
CPC分类号： H01L22/20
摘要： A processing line includes a processing tool, a measurement tool, and an automatic process controller. The processing tool is adapted to process articles. The measurement tool is adapted to measure a characteristic of selected articles at a measurement frequency. The automatic process controller is adapted to change the measurement frequency based on a usage characteristic of the processing tool. A method for monitoring a processing tool includes processing a plurality of articles in the processing tool; measuring a characteristic of selected articles at a measurement frequency; and changing the measurement frequency based on a usage characteristic of the processing tool.
摘要翻译：处理线包括处理工具，测量工具和自动过程控制器。处理工具适于处理物品。测量工具适于测量所选物品在测量频率上的特性。自动处理控制器适于基于处理工具的使用特性来改变测量频率。一种用于监视处理工具的方法包括处理处理工具中的多个物品; 以测量频率测量所选物品的特性; 以及基于所述处理工具的使用特性来改变测量频率。

5. 发明授权

US06684122B1 Control mechanism for matching process parameters in a multi-chamber process tool 有权
标题翻译：在多室工艺工具中匹配工艺参数的控制机制
公开(公告)号：US06684122B1
公开(公告)日：2004-01-27
申请号：US09476892
申请日：2000-01-03
申请人： Craig W. Christian , Bradley M. Davis , Allen L. Evans
发明人： Craig W. Christian , Bradley M. Davis , Allen L. Evans
IPC分类号： G06F1900
CPC分类号： H01L21/67276 , G05B19/41875 , G05B2219/32182 , G05B2219/37576 , G05B2219/45031 , Y02P90/16 , Y02P90/22
摘要： The invention, in its various aspects and embodiments, is a method and apparatus for controlling the operation of a multi-chamber process tool in a semiconductor fabrication process. The method comprises setting a plurality of operation parameters for the conduct of a predetermined operation in each of a plurality of process chambers in a multi-chamber process tool; performing the predetermined operation in each of the process chambers; examining a physical characteristic of a processed wafer from each of the process chambers; determining from the examined physical characteristics whether the operating conditions in each of the process chambers match; and resetting at least one operating parameter so that the operating conditions in each of the process chambers will match. The apparatus comprises a processing tool, a review station, and a tool controller. The processing tool includes a plurality of process chambers and an operation controller. Each process chamber is capable of performing a predetermined operation defined by a plurality of operating parameters. The operation controller is capable of setting the operating parameter for each of the process chambers. The review station is capable of examining a physical characteristic of a processed wafer from each of the process chambers and outputting the results of the examination. The tool controller is capable of receiving the examination result, determining whether the operating parameters of the process chambers match, and instructing the operation controller to reset at least some of the operating parameters responsive thereto to match the operating conditions in the process chambers.
摘要翻译：本发明在其各个方面和实施例中是用于在半导体制造工艺中控制多室工艺工具的操作的方法和装置。该方法包括在多室处理工具中设置用于在多个处理室中的每一个中执行预定操作的多个操作参数; 在每个处理室中执行预定操作; 从每个处理室检查经处理的晶片的物理特性; 根据所检查的物理特性确定每个处理室中的操作条件是否匹配; 并且重置至少一个操作参数，使得每个处理室中的操作条件将匹配。该装置包括处理工具，检查站和工具控制器。处理工具包括多个处理室和操作控制器。每个处理室能够执行由多个操作参数定义的预定操作。操作控制器能够设置每个处理室的操作参数。检查站能够从每个处理室检查处理的晶片的物理特性，并输出检查结果。工具控制器能够接收检查结果，确定处理室的操作参数是否匹配，并指示操作控制器响应于此来重置至少一些操作参数以匹配处理室中的操作条件。

6. 发明申请

US20090176369A1 LOW-H PLASMA TREATMENT WITH N2 ANNEAL FOR ELECTRONIC MEMORY DEVICES 有权
标题翻译：用于电子存储器件的N2天线的低等离子体处理
公开(公告)号：US20090176369A1
公开(公告)日：2009-07-09
申请号：US11971331
申请日：2008-01-09
申请人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Eric Wilson , Sung Jin Kim , Hieu Trung Pham
发明人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Eric Wilson , Sung Jin Kim , Hieu Trung Pham
IPC分类号： H01L21/44
CPC分类号： H01L21/76877 , H01L21/76814 , H01L21/76828 , H01L21/76834 , H01L21/76883 , Y10S438/902
摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.
摘要翻译：一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

7. 发明授权

US06442054B1 Sense amplifier for content addressable memory 失效
标题翻译：用于内容可寻址存储器的感应放大器
公开(公告)号：US06442054B1
公开(公告)日：2002-08-27
申请号：US09866056
申请日：2001-05-24
申请人： Allen L. Evans , Wen-Kuan Fang
发明人： Allen L. Evans , Wen-Kuan Fang
IPC分类号： G11C1500
CPC分类号： G11C7/062 , G11C15/04
摘要： A sense amplifier includes a first transistor coupled between a match line of a CAM array and a VDD supply terminal. The match line is pre-charged through the first transistor to a voltage equal to a reference voltage minus the first transistor threshold voltage, VT1. The match line is coupled to the source of a second transistor, which has a threshold voltage VT2, wherein VT2>VT1. A dummy line of the CAM array, which is coupled to the gate of the second transistor, is pre-charged to the reference voltage. A storage node, which is coupled to the drain of the second transistor, is pre-charged to the VDD supply voltage. A non-match condition causes the voltage on the match line to be pulled down. When the voltage on the dummy line exceeds the voltage on the match line by VT2, the second transistor turns on, thereby pulling down the storage node.
摘要翻译：读出放大器包括耦合在CAM阵列的匹配线和VDD电源端之间的第一晶体管。匹配线通过第一晶体管预充电到等于参考电压减去第一晶体管阈值电压VT1的电压。匹配线耦合到具有阈值电压VT2的第二晶体管的源极，其中VT2> VT1。耦合到第二晶体管的栅极的CAM阵列的虚拟线被预充电到参考电压。耦合到第二晶体管的漏极的存储节点被预充电到VDD电源电压。不匹配条件导致匹配线上的电压被拉低。当虚线上的电压超过匹配线上的电压VT2时，第二晶体管导通，从而拉下存储节点。

8. 发明授权

US06291253B1 Feedback control of deposition thickness based on polish planarization 有权
标题翻译：基于抛光平面化的沉积厚度的反馈控制
公开(公告)号：US06291253B1
公开(公告)日：2001-09-18
申请号：US09378348
申请日：1999-08-20
申请人： Jeremy Lansford , Allen L. Evans
发明人： Jeremy Lansford , Allen L. Evans
IPC分类号： H01L2100
CPC分类号： H01L21/02164 , B24B37/042 , B24B49/00 , H01L21/31053 , H01L22/12
摘要： The present invention is directed to semiconductor processing operations, and, more particularly, to a method and system for adjusting the thickness of process layers based upon the planarization efficiency of polishing operations. In one embodiment, the invention comprises determining the planarization efficiency of polishing operations, and adjusting the manufactured thickness of a process layer based upon the determined planarization efficiency.
摘要翻译：本发明涉及半导体处理操作，更具体地说，涉及一种基于抛光操作的平坦化效率来调整工艺层厚度的方法和系统。在一个实施例中，本发明包括确定抛光操作的平面化效率，以及基于确定的平坦化效率来调整制造的工艺层的厚度。

9. 发明授权

US5895259A Polysilicon diffusion doping method employing a deposited doped oxide layer with a highly uniform thickness 失效
标题翻译：采用具有高度均匀厚度的沉积掺杂氧化物层的多晶硅扩散掺杂方法
公开(公告)号：US5895259A
公开(公告)日：1999-04-20
申请号：US647637
申请日：1996-05-15
申请人： W. Mark Carter , Allen L. Evans , John G. Zvonar
发明人： W. Mark Carter , Allen L. Evans , John G. Zvonar
IPC分类号： H01L21/28 , H01L21/3215 , H01L21/44
CPC分类号： H01L21/28035 , H01L21/32155 , Y10S148/051 , Y10S438/914 , Y10S438/915
摘要： A polysilicon diffusion doping method which employs a deposited dopant-rich oxide layer with a highly uniform distribution of dopant atoms and thickness. Polysilicon layers 1,500 angstroms thick have been doped, achieving average resistance values of 60 ohms and non-uniformity values of 5 percent. Resistance values were measured using the four-point probe method with probe spacings of 0.10 cm. After a polysilicon layer has been formed upon a surface of a silicon wafer, a dopant-rich oxide layer is deposited upon the polysilicon layer at reduced pressure. The dopant-rich oxide layer is deposited, and serves as a source of dopant atoms during the subsequent diffusion process. The dopant-rich oxide layer is a phosphosilicate glass (PSG) including phosphorus pentoxide (P.sub.2 O.sub.5) and phosphorus trioxide (P.sub.2 O.sub.3) and deposited using a PECVD technique. Following deposition of the dopant-rich oxide layer, the silicon wafer is heated to drive dopant atoms from the dopant-rich oxide layer into the underlying polysilicon layer, and to electrically activate the dopant atoms within the polysilicon layer. The presence of electrically active dopant atoms within the polysilicon layer lowers the electrical resistivity of the polysilicon layer. After the heating step, the dopant-rich oxide layer is removed.
摘要翻译：一种多晶硅扩散掺杂方法，其使用具有掺杂剂原子和厚度的高度均匀分布的沉积的掺杂剂浓的氧化物层。已经掺杂了1500埃厚的多晶硅层，实现了60欧姆的平均电阻值和5％的非均匀性值。使用探针间距为0.10cm的四点探针法测量电阻值。在硅晶片的表面上形成多晶硅层之后，在减压下在多晶硅层上沉积富含掺杂剂的氧化物层。沉积富掺杂剂的氧化物层，并且在随后的扩散过程中用作掺杂剂原子的源。富含掺杂剂的氧化物层是包含五氧化二磷（P 2 O 5）和三氧化磷（P 2 O 3）的磷硅酸盐玻璃（PSG）并使用PECVD技术沉积。在沉积掺杂剂富氧化物层之后，加热硅晶片以将掺杂剂原子从富含掺杂剂的氧化物层驱动到下面的多晶硅层中，并激活多晶硅层内的掺杂剂原子。多晶硅层内电活性掺杂剂原子的存在降低了多晶硅层的电阻率。在加热步骤之后，去除富含掺杂剂的氧化物层。

10. 发明授权

US06271112B1 Interlayer between titanium nitride and high density plasma oxide 有权
标题翻译：氮化钛和高密度等离子体氧化物之间的层间
公开(公告)号：US06271112B1
公开(公告)日：2001-08-07
申请号：US09191763
申请日：1998-11-13
申请人： Christopher L. Wooten , Craig W. Christian , Thomas E. Spikes, Jr. , Allen L. Evans , Tim Z. Hossain
发明人： Christopher L. Wooten , Craig W. Christian , Thomas E. Spikes, Jr. , Allen L. Evans , Tim Z. Hossain
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/32051 , H01L21/76801 , H01L21/76834 , H01L21/76837 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing die loss in a semiconductor fabrication process which employs titanium nitride and HDP oxide is provided. In the fabrication of multilevel interconnect structures, there is a propensity for defect formation in a process in which titanium nitride and HDP oxide layers are in contact along the edge of a semiconductor substrate. A dielectric interlayer is provided which improves the interfacial properties between titanium nitride and HDP oxide and thereby reduces defects caused by delamination at the titanium nitride/HDP oxide interface.
摘要翻译：提供了一种在采用氮化钛和HDP氧化物的半导体制造工艺中减少晶粒损耗的方法。在多层互连结构的制造中，在氮化钛和HDP氧化物层沿着半导体衬底的边缘接触的过程中存在缺陷形成的倾向。提供了一种电介质中间层，其改善了氮化钛和HDP氧化物之间的界面性质，从而减少了由氮化钛/ HDP氧化物界面处的分层引起的缺陷。

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