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1. 发明授权

US06828598B1 Semiconductor device for electro-optic applications, method for manufacturing said device and corresponding semiconductor laser device 有权
标题翻译：用于电光应用的半导体器件，用于制造所述器件的方法和相应的半导体激光器件
公开(公告)号：US06828598B1
公开(公告)日：2004-12-07
申请号：US09653390
申请日：2000-09-01
申请人： Salvatore Coffa , Sebania Libertino , Mario Saggio , Ferruccio Frisina
发明人： Salvatore Coffa , Sebania Libertino , Mario Saggio , Ferruccio Frisina
IPC分类号： H01L3300
CPC分类号： H01S5/305 , H01S3/1603 , H01S3/1628 , H01S5/3004 , H01S5/3068
摘要： A semiconductor device for electro-optic applications includes a rare-earth ions doped P/N junction integrated on a semiconductor substrate. The semiconductor device may be used to obtain laser action in silicon. The rare-earth ions are in a depletion layer of the doped P/N junction, and are for providing a coherent light source cooperating with a waveguide defined by the doped P/N junction. The doped P/N junction may be the base-collector region of a bipolar transistor, and is reverse biased so that the rare-earth ions provide the coherent light.
摘要翻译：用于电光应用的半导体器件包括集成在半导体衬底上的稀土离子掺杂P / N结。半导体器件可用于在硅中获得激光作用。稀土离子在掺杂的P / N结的耗尽层中，并且用于提供与由掺杂的P / N结限定的波导配合的相干光源。掺杂的P / N结可以是双极晶体管的基极 - 集电极区域，并且被反向偏置，使得稀土离子提供相干光。

2. 发明授权

US06433399B1 Infrared detector device of semiconductor material and manufacturing process thereof 有权
标题翻译：半导体材料红外探测器及其制造工艺
公开(公告)号：US06433399B1
公开(公告)日：2002-08-13
申请号：US09415022
申请日：1999-10-07
申请人： Albert Polman , Nicholas Hamelin , Peter Kik , Salvatore Coffa , Ferruccio Frisina , Mario Saggio
发明人： Albert Polman , Nicholas Hamelin , Peter Kik , Salvatore Coffa , Ferruccio Frisina , Mario Saggio
IPC分类号： H01L310232
CPC分类号： G02B6/12004 , H01L31/0352 , H01L31/103
摘要： An infrared detector device having a PN junction formed by a first semiconductor material region doped with rare earth ions and by a second semiconductor material region of opposite doping type. The detector device comprises a waveguide formed by a projecting structure extending on a substrate, including a reflecting layer and laterally delimited by a protection and containment oxide region. At least one portion of the waveguide is formed by the PN junction and has an end fed with light to be detected. The detector device has electrodes disposed laterally to and on the waveguide to enable efficient gathering of charge carriers generated by photoconversion.
摘要翻译：具有由掺杂有稀土离子的第一半导体材料区域和具有相反掺杂型的第二半导体材料区域形成的PN结的红外检测器装置。检测器装置包括由在衬底上延伸的突出结构形成的波导，包括反射层，并由保护和容纳氧化物区域横向界定。波导的至少一部分由PN结形成，并且具有馈送待检测光的端部。检测器装置具有横向设置在波导上的电极，以使得能够有效地收集通过光转换产生的电荷载流子。

3. 发明授权

US5939769A Bipolar power transistor with high collector breakdown voltage and related manufacturing process 失效
标题翻译：具有高集电极击穿电压和相关制造工艺的双极功率晶体管
公开(公告)号：US5939769A
公开(公告)日：1999-08-17
申请号：US904257
申请日：1997-07-31
申请人： Ferruccio Frisina , Salvatore Coffa
发明人： Ferruccio Frisina , Salvatore Coffa
IPC分类号： H01L21/331 , H01L29/06 , H01L29/167 , H01L29/73 , H01L29/732 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66295 , H01L29/0615 , H01L29/167 , H01L29/73 , Y10S148/01 , Y10S438/965
摘要： There is described a bipolar power transistor with high breakdown voltage, obtained in a heavily doped semiconductor substrate of the N type, over which a lightly doped N type layer, constituting a collector region of the transistor, is superimposed. The transistor has a base region comprising a heavily doped P type diffusion, which extends into the lightly doped N type layer from a top surface. The transistor further includes an emitter region constituted by a heavily doped N type diffusion extending from the top surface within said heavily doped P type diffusion. The heavily doped P type diffusion is obtained within a deep lightly doped P type diffusion, extending from said top surface into the lightly doped N type layer and formed with acceptor impurities of aluminum atoms.
摘要翻译：描述了在N型的重掺杂半导体衬底中获得的具有高击穿电压的双极功率晶体管，其上叠加构成晶体管的集电极区的轻掺杂N型层。晶体管具有包括重掺杂P型扩散的基极区，其从顶表面延伸到轻掺杂的N型层中。晶体管还包括由在所述重掺杂P型扩散内的顶表面延伸的重掺杂N型扩散构成的发射极区域。在深掺杂的P型扩散中获得重掺杂的P型扩散，该扩散从所述顶表面延伸到轻掺杂的N型层中，并由铝原子的受主杂质形成。

4. 发明授权

US5569612A Process for manufacturing a bipolar power transistor having a high breakdown voltage 失效
标题翻译：具有高击穿电压的双极性功率晶体管的制造方法
公开(公告)号：US5569612A
公开(公告)日：1996-10-29
申请号：US481890
申请日：1995-06-07
申请人： Ferruccio Frisina , Salvatore Coffa
发明人： Ferruccio Frisina , Salvatore Coffa
IPC分类号： H01L21/331 , H01L29/06 , H01L29/167 , H01L29/73 , H01L29/732 , H01L21/265
CPC分类号： H01L29/66295 , H01L29/0615 , H01L29/167 , H01L29/73 , Y10S148/01 , Y10S438/965
摘要： There is described a bipolar power transistor with high breakdown voltage, obtained in a heavily doped semiconductor substrate of the N type, over which a lightly doped N type layer, constituting a collector region of the transistor, is superimposed. The transistor has a base region comprising a heavily doped P type diffusion, which extends into the lightly doped N type layer from a top surface. The transistor further includes an emitter region constituted by a heavily doped N type diffusion extending from the top surface within said heavily doped P type diffusion. The heavily doped P type diffusion is obtained within a deep lightly doped P type diffusion, extending from said top surface into the lightly doped N type layer and formed with acceptor impurities of aluminum atoms.
摘要翻译：描述了在N型的重掺杂半导体衬底中获得的具有高击穿电压的双极功率晶体管，其上叠加构成晶体管的集电极区的轻掺杂N型层。晶体管具有包括重掺杂P型扩散的基极区，其从顶表面延伸到轻掺杂的N型层中。晶体管还包括由在所述重掺杂P型扩散内的顶表面延伸的重掺杂N型扩散构成的发射极区域。在深掺杂的P型扩散中获得重掺杂的P型扩散，该扩散从所述顶表面延伸到轻掺杂的N型层中，并由铝原子的受主杂质形成。

5. 发明授权

US06943390B2 High-gain photodetector with separated PN junction and rare earth doped region and a method of forming the same 有权
标题翻译：具有分离的PN结和稀土掺杂区的高增益光电探测器及其形成方法
公开(公告)号：US06943390B2
公开(公告)日：2005-09-13
申请号：US10142264
申请日：2002-05-08
申请人： Salvatore Coffa , Sebania Libertino , Ferruccio Frisina
发明人： Salvatore Coffa , Sebania Libertino , Ferruccio Frisina
IPC分类号： H01L31/0288 , H01L31/107 , H01L27/148
CPC分类号： H01L31/107 , H01L31/0288 , Y02B10/10 , Y02E10/50
摘要： The high-gain photodetector is formed in a semiconductor-material body which houses a PN junction and a sensitive region that is doped with rare earths, for example erbium. The PN junction forms an acceleration and gain region separate from the sensitive region. The PN junction is reverse-biased and generates an extensive depletion region accommodating the sensitive region. Thereby, the incident photon having a frequency equal to the absorption frequency of the used rare earth crosses the PN junction, which is transparent to light, can be captured by an erbium ion in the sensitive region, so as to generate a primary electron, which is accelerated towards the PN junction by the electric field present, and can, in turn, generate secondary electrons by impact, according to an avalanche process. Thereby, a single photon can give rise to a cascade of electrons, thus considerably increasing detection efficiency.
摘要翻译：高增益光电检测器形成在容纳PN结的半导体材料体和掺杂有稀土（例如铒）的敏感区域中。 PN结形成与敏感区域分离的加速度和增益区域。 PN结被反向偏置并且产生容纳敏感区域的广泛的耗尽区域。因此，具有等于所使用的稀土的吸收频率的频率的入射光子穿过对光透明的PN结，可以在敏感区域中被铒离子捕获，以便产生一次电子，其中通过存在的电场而朝向PN结加速，并且根据雪崩过程又可以通过冲击产生二次电子。因此，单个光子可以产生级联的电子，从而显着提高检测效率。

6. 发明授权

US09018635B2 Integrated electronic device with edge-termination structure and manufacturing method thereof 有权
标题翻译：具有边缘终端结构的集成电子装置及其制造方法
公开(公告)号：US09018635B2
公开(公告)日：2015-04-28
申请号：US13221778
申请日：2011-08-30
申请人： Ferruccio Frisina , Angelo Magri' , Mario Giuseppe Saggio
发明人： Ferruccio Frisina , Angelo Magri' , Mario Giuseppe Saggio
IPC分类号： H01L29/16 , H01L29/78 , H01L29/267 , H01L29/06 , H01L29/10 , H01L29/40
CPC分类号： H01L29/66666 , H01L21/02529 , H01L21/02532 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0661 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/165 , H01L29/267 , H01L29/402 , H01L29/66431 , H01L29/7811 , H01L29/7813
摘要： An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.
摘要翻译：一种形成在由侧面限定的半导体主体中的集成电子器件的实施例，包括：由第一半导体材料制成的衬底; 由第二半导体材料制成的第一外延区，其覆盖在所述基板上并限定第一表面; 由第三半导体材料制成的第二外延区，其覆盖在第一表面上并与第一外延区接触，第三半导体材料具有比第二半导体材料的带隙窄的带隙; 有源区域，在所述第二外延区域内延伸并容纳至少一个基本电子部件; 以及边缘结构，其布置在所述有源区域和所述侧表面之间，并且包括相对于所述第二外延区域横向布置的介质区域，所述介电区域覆盖所述第一表面并与所述第一外延区域接触。

7. 发明申请

US20120187480A1 PROCESS FOR MANUFACTURING A POWER SEMICONDUCTOR DEVICE HAVING CHARGE-BALANCE COLUMNAR STRUCTURES ON A NON-PLANAR SURFACE, AND CORRESPONDING POWER SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造在非平面表面上具有电荷平衡柱结构的功率半导体器件的工艺以及相应的功率半导体器件
公开(公告)号：US20120187480A1
公开(公告)日：2012-07-26
申请号：US13434741
申请日：2012-03-29
申请人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
发明人： Alfio Guarnera , Mario Giuseppe Saggio , Ferruccio Frisina
IPC分类号： H01L29/78
CPC分类号： H01L29/0634 , H01L21/2003 , H01L21/324 , H01L29/0847 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/8611 , H01L29/872
摘要： An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.
摘要翻译：用于制造功率半导体器件的方法的实施例设想了以下步骤：提供具有顶表面并具有第一导电性的半导体材料体; 在半导体材料的主体内形成具有第二导电类型的柱状区域，以及在顶表面上方的柱状区域的表面延伸; 以及在顶表面附近形成具有第二类型导电性的掺杂区域并与柱状区域接触。掺杂区域至少部分地形成在柱状区域的表面延伸部内; 表面延伸部分和掺杂区域具有非平面的表面图案，特别是具有大致V形的凹槽。

8. 发明授权

US07304335B2 Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performance and high scaling down density 有权
标题翻译：具有双重厚度栅极氧化物的垂直导通和平面结构的MOS器件和用于实现具有改善的静态和动态性能以及高缩小密度的功率垂直MOS晶体管的方法
公开(公告)号：US07304335B2
公开(公告)日：2007-12-04
申请号：US11279967
申请日：2006-04-17
申请人： Angelo Magri' , Ferruccio Frisina , Giuseppe Ferla , Marco Camalleri
发明人： Angelo Magri' , Ferruccio Frisina , Giuseppe Ferla , Marco Camalleri
IPC分类号： H01L29/78 , H01L29/10
CPC分类号： H01L29/7802 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L29/66712
摘要： A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.
摘要翻译：具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

9. 发明授权

US07067363B2 Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performances and high scaling down density 有权
标题翻译：具有双重栅极氧化物的垂直导通和平面结构的MOS器件和用于实现具有改善的静态和动态性能以及高缩小密度的功率垂直MOS晶体管的方法
公开(公告)号：US07067363B2
公开(公告)日：2006-06-27
申请号：US10749134
申请日：2003-12-30
申请人： Angelo Magri′ , Ferruccio Frisina , Giuseppe Ferla , Marco Camalleri
发明人： Angelo Magri′ , Ferruccio Frisina , Giuseppe Ferla , Marco Camalleri
IPC分类号： H01L21/337 , H01L29/80 , H01L31/112
CPC分类号： H01L29/7802 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L29/66712
摘要： A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.
摘要翻译：具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

10. 发明授权

US06809383B2 Method of manufacturing an integrated edge structure for high voltage semiconductor devices, and related integrated edge structure 有权
标题翻译：制造用于高压半导体器件的集成边缘结构的方法以及相关的集成边缘结构
公开(公告)号：US06809383B2
公开(公告)日：2004-10-26
申请号：US09925080
申请日：2001-08-08
申请人： Ferruccio Frisina
发明人： Ferruccio Frisina
IPC分类号： H01L2974
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/66712 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semiconductor layer, a third step of removing portions of the first mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer through the at least one opening, a fifth step of completely removing the first mask and of forming a second semiconductor layer of the first conductivity type over the first semiconductor layer, a sixth step of diffusing the dopant implanted in the first semiconductor layer in order to form a doped region of the second conductivity type in the first and second semiconductor layers. The second step up to the sixth step are repeated at least one time in order to form a final edge structure including a number of superimposed semiconductor layers of the first conductivity type and at least two columns of doped regions of the second conductivity type, the columns being inserted in the number of superimposed semiconductor layers and formed by superimposition of the doped regions subsequently implanted through the mask openings, the column near the high voltage semiconductor device being deeper than the column farther from the high voltage semiconductor device.
摘要翻译：制造高压半导体器件的边缘结构的方法，包括形成第一导电类型的第一半导体层的第一步骤，在第一半导体层的顶表面上形成第一掩模的第二步骤，第三步骤去除所述第一掩模的部分以在其中形成至少一个开口;第四步骤，通过所述至少一个开口在所述第一半导体层中引入第二导电类型的掺杂剂;第五步骤，完全去除所述第一掩模以及在第一半导体层上形成第一导电类型的第二半导体层，第六步骤，在第一半导体层和第二半导体层中形成第二导电类型的掺杂区，。至少第一步的第二步重复至少一次以便形成最终边缘结构，其包括多个第一导电类型的叠加半导体层和至少两列第二导电类型的掺杂区域，列以叠加的半导体层的数量插入并且通过随后通过掩模开口注入的掺杂区的叠加而形成，高压半导体器件附近的列比离高压半导体器件更远的列深。

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