专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06828598B1 Semiconductor device for electro-optic applications, method for manufacturing said device and corresponding semiconductor laser device 有权
标题翻译：用于电光应用的半导体器件，用于制造所述器件的方法和相应的半导体激光器件
公开(公告)号：US06828598B1
公开(公告)日：2004-12-07
申请号：US09653390
申请日：2000-09-01
申请人： Salvatore Coffa , Sebania Libertino , Mario Saggio , Ferruccio Frisina
发明人： Salvatore Coffa , Sebania Libertino , Mario Saggio , Ferruccio Frisina
IPC分类号： H01L3300
CPC分类号： H01S5/305 , H01S3/1603 , H01S3/1628 , H01S5/3004 , H01S5/3068
摘要： A semiconductor device for electro-optic applications includes a rare-earth ions doped P/N junction integrated on a semiconductor substrate. The semiconductor device may be used to obtain laser action in silicon. The rare-earth ions are in a depletion layer of the doped P/N junction, and are for providing a coherent light source cooperating with a waveguide defined by the doped P/N junction. The doped P/N junction may be the base-collector region of a bipolar transistor, and is reverse biased so that the rare-earth ions provide the coherent light.
摘要翻译：用于电光应用的半导体器件包括集成在半导体衬底上的稀土离子掺杂P / N结。半导体器件可用于在硅中获得激光作用。稀土离子在掺杂的P / N结的耗尽层中，并且用于提供与由掺杂的P / N结限定的波导配合的相干光源。掺杂的P / N结可以是双极晶体管的基极 - 集电极区域，并且被反向偏置，使得稀土离子提供相干光。

2. 发明授权

US06943390B2 High-gain photodetector with separated PN junction and rare earth doped region and a method of forming the same 有权
标题翻译：具有分离的PN结和稀土掺杂区的高增益光电探测器及其形成方法
公开(公告)号：US06943390B2
公开(公告)日：2005-09-13
申请号：US10142264
申请日：2002-05-08
申请人： Salvatore Coffa , Sebania Libertino , Ferruccio Frisina
发明人： Salvatore Coffa , Sebania Libertino , Ferruccio Frisina
IPC分类号： H01L31/0288 , H01L31/107 , H01L27/148
CPC分类号： H01L31/107 , H01L31/0288 , Y02B10/10 , Y02E10/50
摘要： The high-gain photodetector is formed in a semiconductor-material body which houses a PN junction and a sensitive region that is doped with rare earths, for example erbium. The PN junction forms an acceleration and gain region separate from the sensitive region. The PN junction is reverse-biased and generates an extensive depletion region accommodating the sensitive region. Thereby, the incident photon having a frequency equal to the absorption frequency of the used rare earth crosses the PN junction, which is transparent to light, can be captured by an erbium ion in the sensitive region, so as to generate a primary electron, which is accelerated towards the PN junction by the electric field present, and can, in turn, generate secondary electrons by impact, according to an avalanche process. Thereby, a single photon can give rise to a cascade of electrons, thus considerably increasing detection efficiency.
摘要翻译：高增益光电检测器形成在容纳PN结的半导体材料体和掺杂有稀土（例如铒）的敏感区域中。 PN结形成与敏感区域分离的加速度和增益区域。 PN结被反向偏置并且产生容纳敏感区域的广泛的耗尽区域。因此，具有等于所使用的稀土的吸收频率的频率的入射光子穿过对光透明的PN结，可以在敏感区域中被铒离子捕获，以便产生一次电子，其中通过存在的电场而朝向PN结加速，并且根据雪崩过程又可以通过冲击产生二次电子。因此，单个光子可以产生级联的电子，从而显着提高检测效率。

3. 发明授权

US06433399B1 Infrared detector device of semiconductor material and manufacturing process thereof 有权
标题翻译：半导体材料红外探测器及其制造工艺
公开(公告)号：US06433399B1
公开(公告)日：2002-08-13
申请号：US09415022
申请日：1999-10-07
申请人： Albert Polman , Nicholas Hamelin , Peter Kik , Salvatore Coffa , Ferruccio Frisina , Mario Saggio
发明人： Albert Polman , Nicholas Hamelin , Peter Kik , Salvatore Coffa , Ferruccio Frisina , Mario Saggio
IPC分类号： H01L310232
CPC分类号： G02B6/12004 , H01L31/0352 , H01L31/103
摘要： An infrared detector device having a PN junction formed by a first semiconductor material region doped with rare earth ions and by a second semiconductor material region of opposite doping type. The detector device comprises a waveguide formed by a projecting structure extending on a substrate, including a reflecting layer and laterally delimited by a protection and containment oxide region. At least one portion of the waveguide is formed by the PN junction and has an end fed with light to be detected. The detector device has electrodes disposed laterally to and on the waveguide to enable efficient gathering of charge carriers generated by photoconversion.
摘要翻译：具有由掺杂有稀土离子的第一半导体材料区域和具有相反掺杂型的第二半导体材料区域形成的PN结的红外检测器装置。检测器装置包括由在衬底上延伸的突出结构形成的波导，包括反射层，并由保护和容纳氧化物区域横向界定。波导的至少一部分由PN结形成，并且具有馈送待检测光的端部。检测器装置具有横向设置在波导上的电极，以使得能够有效地收集通过光转换产生的电荷载流子。

4. 发明授权

US5939769A Bipolar power transistor with high collector breakdown voltage and related manufacturing process 失效
标题翻译：具有高集电极击穿电压和相关制造工艺的双极功率晶体管
公开(公告)号：US5939769A
公开(公告)日：1999-08-17
申请号：US904257
申请日：1997-07-31
申请人： Ferruccio Frisina , Salvatore Coffa
发明人： Ferruccio Frisina , Salvatore Coffa
IPC分类号： H01L21/331 , H01L29/06 , H01L29/167 , H01L29/73 , H01L29/732 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66295 , H01L29/0615 , H01L29/167 , H01L29/73 , Y10S148/01 , Y10S438/965
摘要： There is described a bipolar power transistor with high breakdown voltage, obtained in a heavily doped semiconductor substrate of the N type, over which a lightly doped N type layer, constituting a collector region of the transistor, is superimposed. The transistor has a base region comprising a heavily doped P type diffusion, which extends into the lightly doped N type layer from a top surface. The transistor further includes an emitter region constituted by a heavily doped N type diffusion extending from the top surface within said heavily doped P type diffusion. The heavily doped P type diffusion is obtained within a deep lightly doped P type diffusion, extending from said top surface into the lightly doped N type layer and formed with acceptor impurities of aluminum atoms.
摘要翻译：描述了在N型的重掺杂半导体衬底中获得的具有高击穿电压的双极功率晶体管，其上叠加构成晶体管的集电极区的轻掺杂N型层。晶体管具有包括重掺杂P型扩散的基极区，其从顶表面延伸到轻掺杂的N型层中。晶体管还包括由在所述重掺杂P型扩散内的顶表面延伸的重掺杂N型扩散构成的发射极区域。在深掺杂的P型扩散中获得重掺杂的P型扩散，该扩散从所述顶表面延伸到轻掺杂的N型层中，并由铝原子的受主杂质形成。

5. 发明授权

US5569612A Process for manufacturing a bipolar power transistor having a high breakdown voltage 失效
标题翻译：具有高击穿电压的双极性功率晶体管的制造方法
公开(公告)号：US5569612A
公开(公告)日：1996-10-29
申请号：US481890
申请日：1995-06-07
申请人： Ferruccio Frisina , Salvatore Coffa
发明人： Ferruccio Frisina , Salvatore Coffa
IPC分类号： H01L21/331 , H01L29/06 , H01L29/167 , H01L29/73 , H01L29/732 , H01L21/265
CPC分类号： H01L29/66295 , H01L29/0615 , H01L29/167 , H01L29/73 , Y10S148/01 , Y10S438/965
摘要： There is described a bipolar power transistor with high breakdown voltage, obtained in a heavily doped semiconductor substrate of the N type, over which a lightly doped N type layer, constituting a collector region of the transistor, is superimposed. The transistor has a base region comprising a heavily doped P type diffusion, which extends into the lightly doped N type layer from a top surface. The transistor further includes an emitter region constituted by a heavily doped N type diffusion extending from the top surface within said heavily doped P type diffusion. The heavily doped P type diffusion is obtained within a deep lightly doped P type diffusion, extending from said top surface into the lightly doped N type layer and formed with acceptor impurities of aluminum atoms.
摘要翻译：描述了在N型的重掺杂半导体衬底中获得的具有高击穿电压的双极功率晶体管，其上叠加构成晶体管的集电极区的轻掺杂N型层。晶体管具有包括重掺杂P型扩散的基极区，其从顶表面延伸到轻掺杂的N型层中。晶体管还包括由在所述重掺杂P型扩散内的顶表面延伸的重掺杂N型扩散构成的发射极区域。在深掺杂的P型扩散中获得重掺杂的P型扩散，该扩散从所述顶表面延伸到轻掺杂的N型层中，并由铝原子的受主杂质形成。

6. 发明申请

US20060194391A1 Power electronic device of multi-drain type integrated on a semiconductor substrate and relative manufacturing process 有权
公开(公告)号：US20060194391A1
公开(公告)日：2006-08-31
申请号：US11362435
申请日：2006-02-23
申请人： Mario Saggio , Ferruccio Frisina
发明人： Mario Saggio , Ferruccio Frisina
IPC分类号： H01L21/336
CPC分类号： H01L29/66712 , H01L29/0634 , H01L29/0847 , H01L29/1095
摘要： A power electronic device is integrated on a semiconductor substrate of a first type of conductivity. The device includes a plurality of elemental units, and each elemental unit includes a body region of a second type of conductivity which is realized on a semiconductor layer of the first type of conductivity formed on the semiconductor substrate, and a column region of the first type of conductivity which is realized in said semiconductor layer below the body region. The semiconductor layer includes multiple semiconductor layers which overlap each other. The resistivity of each layer is different from that of the other layers. The column region includes a plurality of doped sub-regions, each realized in one of the semiconductor layers. The amount of charge of each doped sub-region balances the amount of charge of the corresponding semiconductor layer in which each doped sub-region is realized.

7. 发明授权

US07071062B2 Integrated device with Schottky diode and MOS transistor and related manufacturing process 有权
标题翻译：集成器件采用肖特基二极管和MOS晶体管及相关制造工艺
公开(公告)号：US07071062B2
公开(公告)日：2006-07-04
申请号：US11023957
申请日：2004-12-28
申请人： Mario Saggio , Ferruccio Frisina
发明人： Mario Saggio , Ferruccio Frisina
IPC分类号： H01L21/336
CPC分类号： H01L29/66712 , H01L29/0634 , H01L29/1095 , H01L29/42376 , H01L29/4238 , H01L29/7806
摘要： An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate of a first conductivity type is shown. The device comprises a plurality of body region stripes of a second conductivity type which are adjacent and parallel to each other, a first metal layer placed over said substrate and a second metal layer placed under said substrate. The device comprises a plurality of elementary structures parallel to each other each one of which comprises first zones provided with a silicon oxide layer placed over a portion of the substrate which is comprised between two adjacent body region stripes, a polysilicon layer superimposed to the silicon oxide layer, a dielectric layer placed over and around the polysilicon layer. Some body region stripes comprise source regions of the first conductivity type which are placed adjacent to the first zones of the elementary structures to form elementary cells of said MOS transistor. The elementary structures and the body regions stripes extend longitudinally in a transversal way to the formation of the channel in the elementary cells of the MOS transistor and the first metal layer contacts the source regions. At least one elementary structure comprises at least a second zone adapted to allow the direct contact between the first metal layer and the underlying substrate portion arranged between two adjacent body regions stripes to perform the Schottky diode.
摘要翻译：示出了包括形成在第一导电类型的半导体衬底上的MOS晶体管和肖特基二极管的集成器件。该装置包括彼此相邻并平行的第二导电类型的多个体区条纹，放置在所述基底上的第一金属层和置于所述基底下的第二金属层。该器件包括彼此平行的多个基本结构，每个基本结构包括第一区域，该第一区域设置有位于两个相邻体区条纹之间的衬底的一部分上的氧化硅层，叠加到氧化硅上的多晶硅层层，放置在多晶硅层上方和周围的介电层。一些体区条纹包括与基本结构的第一区相邻放置的第一导电类型的源区，以形成所述MOS晶体管的元件。基本结构和体区条纹以横向方式纵向延伸，以在MOS晶体管的基本单元中形成沟道，并且第一金属层接触源极区。至少一个基本结构包括至少第二区域，适于允许第一金属层与布置在两个相邻体区条纹之间的下面的基底部分之间的直接接触以执行肖特基二极管。

8. 发明授权

US06404010B2 MOS technology power device 有权
标题翻译： MOS技术电源设备
公开(公告)号：US06404010B2
公开(公告)日：2002-06-11
申请号：US09860809
申请日：2001-05-17
申请人： Mario Saggio , Ferruccio Frisina , Angelo Magri'
发明人： Mario Saggio , Ferruccio Frisina , Angelo Magri'
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/0615 , H01L29/0619 , H01L29/0634
摘要： A MOS technology power device is described which comprises a plurality of elementary active units and a part of said power device which is placed between zones where the elementary active units are formed. The part of the power device comprises at least two heavily doped body regions of a first conductivity type which are formed in a semiconductor layer of a second conductivity type, a first lightly doped semiconductor region of the first conductivity type which is placed laterally between the two body regions. The first semiconductor region is placed under a succession of a thick silicon oxide layer, a polysilicon layer and a metal layer. A plurality of second lightly doped semiconductor regions of the first conductivity type are placed under said at least two heavily doped body regions and under said first lightly doped semiconductor region of the first conductivity type, each region of said plurality of second lightly doped semiconductor regions of the first conductivity type being separated from the other by portions of said semiconductor layer of the second conductivity type.
摘要翻译：描述了MOS技术功率器件，其包括多个基本有源单元和放置在形成基本有源单元的区域之间的所述功率器件的一部分。功率器件的一部分包括形成在第二导电类型的半导体层中的第一导电类型的至少两个重掺杂体区域，第一导电类型的第一轻掺杂半导体区域横向放置在两者之间身体区域。第一半导体区域被放置在一连串厚的氧化硅层，多晶硅层和金属层之下。第一导电类型的多个第二轻掺杂半导体区域被放置在所述至少两个重掺杂体区域的下方，并且在所述第一导电类型的所述第一轻掺杂半导体区域的下方，所述多个第二轻掺杂半导体区域的每个区域所述第一导电类型通过所述第二导电类型的所述半导体层的一部分与另一个分离。

9. 发明申请

US20050118766A1 Integrated device with Schottky diode and MOS transistor and related manufacturing process 有权
标题翻译：集成器件采用肖特基二极管和MOS晶体管及相关制造工艺
公开(公告)号：US20050118766A1
公开(公告)日：2005-06-02
申请号：US11023957
申请日：2004-12-28
申请人： Mario Saggio , Ferruccio Frisina
发明人： Mario Saggio , Ferruccio Frisina
IPC分类号： H01L21/336 , H01L29/06 , H01L29/78
CPC分类号： H01L29/66712 , H01L29/0634 , H01L29/1095 , H01L29/42376 , H01L29/4238 , H01L29/7806
摘要： An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate of a first conductivity type is shown. The device comprises a plurality of body region stripes of a second conductivity type which are adjacent and parallel to each other, a first metal layer placed over said substrate and a second metal layer placed under said substrate. The device comprises a plurality of elementary structures parallel to each other each one of which comprises first zones provided with a silicon oxide layer placed over a portion of the substrate which is comprised between two adjacent body region stripes, a polysilicon layer superimposed to the silicon oxide layer, a dielectric layer placed over and around the polysilicon layer. Some body region stripes comprise source regions of the first conductivity type which are placed adjacent to the first zones of the elementary structures to form elementary cells of said MOS transistor. The elementary structures and the body regions stripes extend longitudinally in a transversal way to the formation of the channel in the elementary cells of the MOS transistor and the first metal layer contacts the source regions. At least one elementary structure comprises at least a second zone adapted to allow the direct contact between the first metal layer and the underlying substrate portion arranged between two adjacent body regions stripes to perform the Schottky diode.
摘要翻译：示出了包括形成在第一导电类型的半导体衬底上的MOS晶体管和肖特基二极管的集成器件。该装置包括彼此相邻并平行的第二导电类型的多个体区条纹，放置在所述基底上的第一金属层和置于所述基底下的第二金属层。该器件包括彼此平行的多个基本结构，每个基本结构包括第一区域，该第一区域设置有位于两个相邻体区条纹之间的衬底的一部分上的氧化硅层，叠加到氧化硅上的多晶硅层层，放置在多晶硅层上方和周围的介电层。一些体区条纹包括与基本结构的第一区相邻放置的第一导电类型的源区，以形成所述MOS晶体管的元件。基本结构和体区条纹以横向方式纵向延伸，以在MOS晶体管的基本单元中形成沟道，并且第一金属层接触源极区。至少一个基本结构包括至少第二区域，其适于允许第一金属层与布置在两个相邻体区条纹之间的下面的衬底部分之间的直接接触以执行肖特基二极管。

10. 发明申请

US20080001223A1 Process for manufacturing a charge-balance power diode and an edge-termination structure for a charge-balance semiconductor power device 有权
标题翻译：用于制造电荷平衡功率二极管的工艺和用于电荷平衡半导体功率器件的边缘终端结构
公开(公告)号：US20080001223A1
公开(公告)日：2008-01-03
申请号：US11824169
申请日：2007-06-28
申请人： Mario Saggio , Domenico Murabito , Ferruccio Frisina
发明人： Mario Saggio , Domenico Murabito , Ferruccio Frisina
IPC分类号： H01L21/336 , H01L29/768
CPC分类号： H01L29/7811 , H01L21/324 , H01L29/0615 , H01L29/0634 , H01L29/0661 , H01L29/0692 , H01L29/0847 , H01L29/41766 , H01L29/66128 , H01L29/66727 , H01L29/66734 , H01L29/73 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/8611 , H01L29/872
摘要： An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top surface and inside an active portion of the body; and forming an edge-termination structure. The edge-termination structure is formed by: a ring region having the first type of conductivity and a first doping level, set within a peripheral edge portion of the body and electrically connected to the active region; and a guard region, having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface and connecting the active region to the ring region. The process further envisages the steps of: forming a surface layer having the first type of conductivity on the first top surface, also at the peripheral edge portion, in contact with the guard region; and etching the surface layer in order to remove it above the edge portion in such a manner that the etch terminates inside the guard region.
摘要翻译：制造半导体功率器件的方法的一个实施例设想了以下步骤：提供由具有第一顶表面的半导体材料制成的本体; 在所述第一顶表面附近和所述主体的活动部分内部形成具有第一类型导电性的有源区; 并形成边缘终端结构。边缘终端结构通过以下方式形成：具有第一类型的导电性和第一掺杂水平的环形区域，其设置在主体的外围边缘部分内并电连接到有源区域; 以及保护区，其具有高于第一掺杂级的第一类型的导电性和第二掺杂级，设置在第一顶表面附近并将有源区连接到环区。该方法进一步设想了以下步骤：在第一顶表面上形成具有第一类型导电性的表面层，也在周边边缘部分形成与保护区域接触的表面层; 并且蚀刻表面层以便以这样的方式将其去除边缘部分，使得蚀刻终止于保护区域内。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式