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1. 发明授权

US09018635B2 Integrated electronic device with edge-termination structure and manufacturing method thereof 有权
标题翻译：具有边缘终端结构的集成电子装置及其制造方法
公开(公告)号：US09018635B2
公开(公告)日：2015-04-28
申请号：US13221778
申请日：2011-08-30
申请人： Ferruccio Frisina , Angelo Magri' , Mario Giuseppe Saggio
发明人： Ferruccio Frisina , Angelo Magri' , Mario Giuseppe Saggio
IPC分类号： H01L29/16 , H01L29/78 , H01L29/267 , H01L29/06 , H01L29/10 , H01L29/40
CPC分类号： H01L29/66666 , H01L21/02529 , H01L21/02532 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0661 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/165 , H01L29/267 , H01L29/402 , H01L29/66431 , H01L29/7811 , H01L29/7813
摘要： An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.
摘要翻译：一种形成在由侧面限定的半导体主体中的集成电子器件的实施例，包括：由第一半导体材料制成的衬底; 由第二半导体材料制成的第一外延区，其覆盖在所述基板上并限定第一表面; 由第三半导体材料制成的第二外延区，其覆盖在第一表面上并与第一外延区接触，第三半导体材料具有比第二半导体材料的带隙窄的带隙; 有源区域，在所述第二外延区域内延伸并容纳至少一个基本电子部件; 以及边缘结构，其布置在所述有源区域和所述侧表面之间，并且包括相对于所述第二外延区域横向布置的介质区域，所述介电区域覆盖所述第一表面并与所述第一外延区域接触。

2. 发明授权

US08653590B2 Vertical-conduction integrated electronic device and method for manufacturing thereof 有权
公开(公告)号：US08653590B2
公开(公告)日：2014-02-18
申请号：US13221694
申请日：2011-08-30
申请人： Ferruccio Frisina , Mario Giuseppe Saggio , Angelo Magri'
发明人： Ferruccio Frisina , Mario Giuseppe Saggio , Angelo Magri'
IPC分类号： H01L29/78
CPC分类号： H01L29/7806 , H01L21/02573 , H01L21/046 , H01L21/265 , H01L29/0619 , H01L29/0821 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/165 , H01L29/267 , H01L29/66068 , H01L29/732 , H01L29/7371 , H01L29/7802 , H01L29/7804 , H01L29/7813 , H01L29/861 , H01L29/872
摘要： An embodiment of a vertical-conduction integrated electronic device formed in a body of semiconductor material which includes: a substrate made of a first semiconductor material and with a first type of conductivity, the first semiconductor material having a first bandgap; an epitaxial region made of the first semiconductor material and with the first type of conductivity, which overlies the substrate and defines a first surface; and a first epitaxial layer made of a second semiconductor material, which overlies the first surface and is in direct contact with the epitaxial region, the second semiconductor material having a second bandgap narrower than the first bandgap. The body moreover includes a deep region of a second type of conductivity, extending underneath the first surface and within the epitaxial region.

3. 发明授权

US07304335B2 Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performance and high scaling down density 有权
标题翻译：具有双重厚度栅极氧化物的垂直导通和平面结构的MOS器件和用于实现具有改善的静态和动态性能以及高缩小密度的功率垂直MOS晶体管的方法
公开(公告)号：US07304335B2
公开(公告)日：2007-12-04
申请号：US11279967
申请日：2006-04-17
申请人： Angelo Magri' , Ferruccio Frisina , Giuseppe Ferla , Marco Camalleri
发明人： Angelo Magri' , Ferruccio Frisina , Giuseppe Ferla , Marco Camalleri
IPC分类号： H01L29/78 , H01L29/10
CPC分类号： H01L29/7802 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L29/66712
摘要： A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.
摘要翻译：具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

4. 发明授权

US06404010B2 MOS technology power device 有权
标题翻译： MOS技术电源设备
公开(公告)号：US06404010B2
公开(公告)日：2002-06-11
申请号：US09860809
申请日：2001-05-17
申请人： Mario Saggio , Ferruccio Frisina , Angelo Magri'
发明人： Mario Saggio , Ferruccio Frisina , Angelo Magri'
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/0615 , H01L29/0619 , H01L29/0634
摘要： A MOS technology power device is described which comprises a plurality of elementary active units and a part of said power device which is placed between zones where the elementary active units are formed. The part of the power device comprises at least two heavily doped body regions of a first conductivity type which are formed in a semiconductor layer of a second conductivity type, a first lightly doped semiconductor region of the first conductivity type which is placed laterally between the two body regions. The first semiconductor region is placed under a succession of a thick silicon oxide layer, a polysilicon layer and a metal layer. A plurality of second lightly doped semiconductor regions of the first conductivity type are placed under said at least two heavily doped body regions and under said first lightly doped semiconductor region of the first conductivity type, each region of said plurality of second lightly doped semiconductor regions of the first conductivity type being separated from the other by portions of said semiconductor layer of the second conductivity type.
摘要翻译：描述了MOS技术功率器件，其包括多个基本有源单元和放置在形成基本有源单元的区域之间的所述功率器件的一部分。功率器件的一部分包括形成在第二导电类型的半导体层中的第一导电类型的至少两个重掺杂体区域，第一导电类型的第一轻掺杂半导体区域横向放置在两者之间身体区域。第一半导体区域被放置在一连串厚的氧化硅层，多晶硅层和金属层之下。第一导电类型的多个第二轻掺杂半导体区域被放置在所述至少两个重掺杂体区域的下方，并且在所述第一导电类型的所述第一轻掺杂半导体区域的下方，所述多个第二轻掺杂半导体区域的每个区域所述第一导电类型通过所述第二导电类型的所述半导体层的一部分与另一个分离。

5. 发明授权

US6040609A Process for integrating, in a single semiconductor chip, MOS technology devices with different threshold voltages 有权
标题翻译：在单个半导体芯片中集成具有不同阈值电压的MOS技术器件的工艺
公开(公告)号：US6040609A
公开(公告)日：2000-03-21
申请号：US178369
申请日：1998-10-23
申请人： Ferruccio Frisina , Davide Bolognesi , Angelo Magri'
发明人： Ferruccio Frisina , Davide Bolognesi , Angelo Magri'
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/78 , H01L29/76
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/82345 , H01L27/088 , H01L29/0696 , H01L29/4238 , H01L29/7802 , H01L29/1095
摘要： Process for integrating in a same MOS technology devices with different threshold voltages. Simultaneously forming on a semiconductor material layer of at least two gate electrodes for at least two MOS devices, said gate electrodes comprising substantially rectilinear portions and corners, each gate electrode having a respective corner density for unit area. Selectively introducing in the semiconductor material layer a dopant for the simultaneous formation of respective channel regions for said at least two MOS devices, said channel regions extending under the respective gate electrode, said selective introduction using as a mask the respective gate electrodes so that said channel regions have, at the corners of the respective gate electrode, a dopant concentration lower than that at the substantially rectilinear portions. Said two MOS devices consequently have respective threshold voltages that depend on the corner density for unit area and on the aperture angles of the corner of the respective gate electrodes.
摘要翻译：用于集成在具有不同阈值电压的相同MOS技术设备中的过程。同时在用于至少两个MOS器件的至少两个栅电极的半导体材料层上形成，所述栅电极基本上包括直线部分和拐角，每个栅电极具有单位面积的相应角密度。在半导体材料层中选择性地引入用于同时形成用于所述至少两个MOS器件的各个沟道区的掺杂剂，所述沟道区在相应的栅极下方延伸，所述选择性引入使用各个栅电极作为掩模，使得所述沟道区域在各个栅电极的角部处具有低于基本上直线部分处的掺杂浓度。所述两个MOS器件因此具有取决于单位面积的角密度和各个栅电极的角的孔径角的各自的阈值电压。

6. 发明授权

US5981998A Single feature size MOS technology power device 失效
公开(公告)号：US5981998A
公开(公告)日：1999-11-09
申请号：US739465
申请日：1996-10-29
申请人： Ferruccio Frisina , Angelo Magri' , Giuseppe Ferla , Richard A. Blanchard
发明人： Ferruccio Frisina , Angelo Magri' , Giuseppe Ferla , Richard A. Blanchard
IPC分类号： H01L29/74 , H01L21/331 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/749 , H01L29/78 , H01L29/00
CPC分类号： H01L29/66333 , H01L29/0696 , H01L29/1095 , H01L29/7802 , H01L29/0847
摘要： A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.

7. 发明申请

US20070102725A1 Insulated gate planar integrated power device with co-integrated Schottky diode and process 有权
标题翻译：具有共同集成肖特基二极管和工艺的绝缘栅平面集成功率器件
公开(公告)号：US20070102725A1
公开(公告)日：2007-05-10
申请号：US11520210
申请日：2006-09-12
申请人： Angelo Magri' , Ferruccio Frisina
发明人： Angelo Magri' , Ferruccio Frisina
IPC分类号： H01L29/74
CPC分类号： H01L29/66719 , H01L21/26586 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/66712 , H01L29/66727 , H01L29/7806 , H01L29/7839 , H01L29/872
摘要： A process for integrating a Schottky contact inside the apertures of the elementary cells that constitute the integrated structure of the insulated gate power device in a totally self-alignment manner does not requires a dedicated masking step. This overcomes the limits to the possibility of increasing the packing density of the cellular structure of the integrated power device, while permitting improved performances of the co-integrated Schottky diode under inverse polarization of the device and producing other advantages. A planar integrated insulated gate power device with high packing density of the elementary cells that compose it, having a Schottky diode electrically in parallel to the co-integrated device, is also disclosed.
摘要翻译：以完全自对准的方式将构成绝缘栅功率器件的集成结构的单元的孔内的肖特基接触集成在一起的处理不需要专用的掩蔽步骤。这克服了增加集成功率器件的蜂窝结构的封装密度的可能性的限制，同时可以在器件的反极化下提高共同集成的肖特基二极管的性能并产生其他优点。还公开了一种平面集成绝缘栅功率器件，其具有构成该元件的单元的高封装密度，其具有与并联器件并联的肖特基二极管。

8. 发明授权

US06566690B2 Single feature size MOS technology power device 有权
标题翻译：单功能尺寸MOS技术电源设备
公开(公告)号：US06566690B2
公开(公告)日：2003-05-20
申请号：US09427236
申请日：1999-10-26
申请人： Angelo Magri' , Ferruccio Frisina , Giuseppe Ferla
发明人： Angelo Magri' , Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L2974
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/0847 , H01L29/0869 , H01L29/1095 , H01L29/66333
摘要： A MOS technology power device includes a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.
摘要翻译： MOS技术功率器件包括第一导电类型的半导体材料层，覆盖半导体材料层的导电绝缘栅极层和多个基本功能单元。导电绝缘栅层包括置于半导体材料层上方的第一绝缘材料层，位于第一绝缘材料层上方的导电材料层和置于导电材料层上方的第二绝缘材料层。每个基本功能单元包括形成在半导体材料层中的第二导电类型的细长体区域。每个基本功能单元还包括在细长体区域上方延伸的绝缘栅极层中的细长窗口。每个细长体区域包括掺杂有第一导电类型的掺杂剂的源区，插入有细长体区的一部分，其中不提供第一导电类型的掺杂剂。 MOS技术功率器件还包括多个绝缘材料侧壁间隔物，其沿着每个细长窗口的细长边缘设置在半导体材料层之上，以密封绝缘栅极层中每个细长窗口的边缘与设置在绝缘栅极上的源极金属层层和半导体材料层。源极金属层沿着细长主体区域的长度通过每个细长窗口接触每个体区域和每个源极区域。

9. 发明授权

US06548864B2 High density MOS technology power device 有权
标题翻译：高密度MOS技术电源设备
公开(公告)号：US06548864B2
公开(公告)日：2003-04-15
申请号：US09426510
申请日：1999-10-26
申请人： Angelo Magri' , Ferruccio Frisina , Giuseppe Ferla
发明人： Angelo Magri' , Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L2994
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/0847 , H01L29/0869 , H01L29/1095 , H01L29/66712
摘要： A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window. The second insulating material layer includes a second elongated window extending above each elongated body region. The second insulating material layer seals the edges of the conductive material layer from a source metal layer disposed over the second insulating material layer. The source metal layer contacts each body region and each source region through each second elongated window along the length of the elongated body region.
摘要翻译： MOS技术功率器件包括第一导电类型的半导体材料层，多个基本功能单元，放置在半导体材料层上方的第一绝缘材料层和放置在第一绝缘材料层上方的导电材料层。每个基本功能单元包括形成在半导体材料层中的第二导电类型的细长体区域。每个基本功能单元还包括在细长主体区域上方延伸的导电材料层中的第一细长窗口。每个细长体区域包括掺杂有第一导电类型的掺杂剂的源区，插入有细长体区的一部分，其中不提供第一导电类型的掺杂剂。 MOS技术功率器件还包括设置在导电材料层上方并沿着第一细长窗的细长边缘设置的第二绝缘材料层。第二绝缘材料层包括在每个细长体区域之上延伸的第二细长窗口。第二绝缘材料层将导电材料层的边缘与设置在第二绝缘材料层上的源极金属层密封。源金属层沿着细长主体区域的长度通过每个第二细长窗口接触每个体区域和每个源区域。

10. 发明申请

US20050139906A1 Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performances and high scaling down density 有权
标题翻译：具有双重栅极氧化物的垂直导通和平面结构的MOS器件和用于实现具有改善的静态和动态性能以及高缩小密度的功率垂直MOS晶体管的方法
公开(公告)号：US20050139906A1
公开(公告)日：2005-06-30
申请号：US10749134
申请日：2003-12-30
申请人： Angelo Magri' , Ferruccio Frisina , Giuseppe Ferla , Marco Camalleri
发明人： Angelo Magri' , Ferruccio Frisina , Giuseppe Ferla , Marco Camalleri
IPC分类号： H01L21/336 , H01L29/08 , H01L29/423 , H01L29/78 , H01L21/8238 , H01L29/94
CPC分类号： H01L29/7802 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L29/66712
摘要： A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.
摘要翻译：具有双厚度栅极氧化物的垂直导通和平面结构的MOS器件包括在半导体衬底中包括间隔开的有源区并在其间限定JFET区的半导体衬底。 JFET区域还在间隔开的有效区域之间形成通道。栅极氧化物在半导体衬底上，并且包括在有源区上具有第一厚度的第一部分和JFET区的周边，以及在JFET区的中心区上具有第二厚度的第二部分。第二厚度大于第一厚度。 JFET区域还包括在栅极氧化物的第二部分下面的富集区域。

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