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1. 发明申请

US20060194391A1 Power electronic device of multi-drain type integrated on a semiconductor substrate and relative manufacturing process 有权
公开(公告)号：US20060194391A1
公开(公告)日：2006-08-31
申请号：US11362435
申请日：2006-02-23
申请人： Mario Saggio , Ferruccio Frisina
发明人： Mario Saggio , Ferruccio Frisina
IPC分类号： H01L21/336
CPC分类号： H01L29/66712 , H01L29/0634 , H01L29/0847 , H01L29/1095
摘要： A power electronic device is integrated on a semiconductor substrate of a first type of conductivity. The device includes a plurality of elemental units, and each elemental unit includes a body region of a second type of conductivity which is realized on a semiconductor layer of the first type of conductivity formed on the semiconductor substrate, and a column region of the first type of conductivity which is realized in said semiconductor layer below the body region. The semiconductor layer includes multiple semiconductor layers which overlap each other. The resistivity of each layer is different from that of the other layers. The column region includes a plurality of doped sub-regions, each realized in one of the semiconductor layers. The amount of charge of each doped sub-region balances the amount of charge of the corresponding semiconductor layer in which each doped sub-region is realized.

2. 发明授权

US07071062B2 Integrated device with Schottky diode and MOS transistor and related manufacturing process 有权
标题翻译：集成器件采用肖特基二极管和MOS晶体管及相关制造工艺
公开(公告)号：US07071062B2
公开(公告)日：2006-07-04
申请号：US11023957
申请日：2004-12-28
申请人： Mario Saggio , Ferruccio Frisina
发明人： Mario Saggio , Ferruccio Frisina
IPC分类号： H01L21/336
CPC分类号： H01L29/66712 , H01L29/0634 , H01L29/1095 , H01L29/42376 , H01L29/4238 , H01L29/7806
摘要： An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate of a first conductivity type is shown. The device comprises a plurality of body region stripes of a second conductivity type which are adjacent and parallel to each other, a first metal layer placed over said substrate and a second metal layer placed under said substrate. The device comprises a plurality of elementary structures parallel to each other each one of which comprises first zones provided with a silicon oxide layer placed over a portion of the substrate which is comprised between two adjacent body region stripes, a polysilicon layer superimposed to the silicon oxide layer, a dielectric layer placed over and around the polysilicon layer. Some body region stripes comprise source regions of the first conductivity type which are placed adjacent to the first zones of the elementary structures to form elementary cells of said MOS transistor. The elementary structures and the body regions stripes extend longitudinally in a transversal way to the formation of the channel in the elementary cells of the MOS transistor and the first metal layer contacts the source regions. At least one elementary structure comprises at least a second zone adapted to allow the direct contact between the first metal layer and the underlying substrate portion arranged between two adjacent body regions stripes to perform the Schottky diode.
摘要翻译：示出了包括形成在第一导电类型的半导体衬底上的MOS晶体管和肖特基二极管的集成器件。该装置包括彼此相邻并平行的第二导电类型的多个体区条纹，放置在所述基底上的第一金属层和置于所述基底下的第二金属层。该器件包括彼此平行的多个基本结构，每个基本结构包括第一区域，该第一区域设置有位于两个相邻体区条纹之间的衬底的一部分上的氧化硅层，叠加到氧化硅上的多晶硅层层，放置在多晶硅层上方和周围的介电层。一些体区条纹包括与基本结构的第一区相邻放置的第一导电类型的源区，以形成所述MOS晶体管的元件。基本结构和体区条纹以横向方式纵向延伸，以在MOS晶体管的基本单元中形成沟道，并且第一金属层接触源极区。至少一个基本结构包括至少第二区域，适于允许第一金属层与布置在两个相邻体区条纹之间的下面的基底部分之间的直接接触以执行肖特基二极管。

3. 发明申请

US20060245258A1 Integrated power device having a start-up structure 有权
标题翻译：具有起动结构的集成动力装置
公开(公告)号：US20060245258A1
公开(公告)日：2006-11-02
申请号：US11396411
申请日：2006-03-31
申请人： Mario Saggio , Antonino Minnolo , Rosalia Germana
发明人： Mario Saggio , Antonino Minnolo , Rosalia Germana
IPC分类号： G11C11/34
CPC分类号： H01L29/0634 , H01L21/823487 , H01L27/088 , H01L29/1095 , H01L29/7803 , H01L29/7811
摘要： An integrated power device includes a semiconductor body of a first conductivity type comprising a first region accommodating a start-up structure, and a second region accommodating a power structure. The two structures are separated from one another by an edge structure and are arranged in a mirror configuration with respect to a symmetry line of the edge structure. Both the start-up structure and the power structure are obtained using MOSFET devices. Both MOSFET devices are multi-drain MOSFET devices, having mesh regions, source regions and gate regions separated from one another. In addition, both MOSFET devices have drain regions delimited by columns that repeat periodically at a fixed distance. Between the two MOSFET devices there is an electrical insulation of at least 25 V.
摘要翻译：集成的功率器件包括第一导电类型的半导体本体，包括容纳启动结构的第一区域和容纳功率结构的第二区域。这两个结构通过边缘结构彼此分离，并且相对于边缘结构的对称线布置成反射镜构造。启动结构和功率结构均使用MOSFET器件获得。两个MOSFET器件都是多漏极MOSFET器件，其具有彼此分离的网格区域，源极区域和栅极区域。另外，两个MOSFET器件具有由固定距离周期性重复的列限定的漏极区域。在两个MOSFET器件之间，电绝缘至少为25 V.

4. 发明申请

US20050118766A1 Integrated device with Schottky diode and MOS transistor and related manufacturing process 有权
标题翻译：集成器件采用肖特基二极管和MOS晶体管及相关制造工艺
公开(公告)号：US20050118766A1
公开(公告)日：2005-06-02
申请号：US11023957
申请日：2004-12-28
申请人： Mario Saggio , Ferruccio Frisina
发明人： Mario Saggio , Ferruccio Frisina
IPC分类号： H01L21/336 , H01L29/06 , H01L29/78
CPC分类号： H01L29/66712 , H01L29/0634 , H01L29/1095 , H01L29/42376 , H01L29/4238 , H01L29/7806
摘要： An integrated device comprising a MOS transistor and a Schottky diode which are formed on a semiconductor substrate of a first conductivity type is shown. The device comprises a plurality of body region stripes of a second conductivity type which are adjacent and parallel to each other, a first metal layer placed over said substrate and a second metal layer placed under said substrate. The device comprises a plurality of elementary structures parallel to each other each one of which comprises first zones provided with a silicon oxide layer placed over a portion of the substrate which is comprised between two adjacent body region stripes, a polysilicon layer superimposed to the silicon oxide layer, a dielectric layer placed over and around the polysilicon layer. Some body region stripes comprise source regions of the first conductivity type which are placed adjacent to the first zones of the elementary structures to form elementary cells of said MOS transistor. The elementary structures and the body regions stripes extend longitudinally in a transversal way to the formation of the channel in the elementary cells of the MOS transistor and the first metal layer contacts the source regions. At least one elementary structure comprises at least a second zone adapted to allow the direct contact between the first metal layer and the underlying substrate portion arranged between two adjacent body regions stripes to perform the Schottky diode.
摘要翻译：示出了包括形成在第一导电类型的半导体衬底上的MOS晶体管和肖特基二极管的集成器件。该装置包括彼此相邻并平行的第二导电类型的多个体区条纹，放置在所述基底上的第一金属层和置于所述基底下的第二金属层。该器件包括彼此平行的多个基本结构，每个基本结构包括第一区域，该第一区域设置有位于两个相邻体区条纹之间的衬底的一部分上的氧化硅层，叠加到氧化硅上的多晶硅层层，放置在多晶硅层上方和周围的介电层。一些体区条纹包括与基本结构的第一区相邻放置的第一导电类型的源区，以形成所述MOS晶体管的元件。基本结构和体区条纹以横向方式纵向延伸，以在MOS晶体管的基本单元中形成沟道，并且第一金属层接触源极区。至少一个基本结构包括至少第二区域，其适于允许第一金属层与布置在两个相邻体区条纹之间的下面的衬底部分之间的直接接触以执行肖特基二极管。

5. 发明授权

US06828598B1 Semiconductor device for electro-optic applications, method for manufacturing said device and corresponding semiconductor laser device 有权
标题翻译：用于电光应用的半导体器件，用于制造所述器件的方法和相应的半导体激光器件
公开(公告)号：US06828598B1
公开(公告)日：2004-12-07
申请号：US09653390
申请日：2000-09-01
申请人： Salvatore Coffa , Sebania Libertino , Mario Saggio , Ferruccio Frisina
发明人： Salvatore Coffa , Sebania Libertino , Mario Saggio , Ferruccio Frisina
IPC分类号： H01L3300
CPC分类号： H01S5/305 , H01S3/1603 , H01S3/1628 , H01S5/3004 , H01S5/3068
摘要： A semiconductor device for electro-optic applications includes a rare-earth ions doped P/N junction integrated on a semiconductor substrate. The semiconductor device may be used to obtain laser action in silicon. The rare-earth ions are in a depletion layer of the doped P/N junction, and are for providing a coherent light source cooperating with a waveguide defined by the doped P/N junction. The doped P/N junction may be the base-collector region of a bipolar transistor, and is reverse biased so that the rare-earth ions provide the coherent light.
摘要翻译：用于电光应用的半导体器件包括集成在半导体衬底上的稀土离子掺杂P / N结。半导体器件可用于在硅中获得激光作用。稀土离子在掺杂的P / N结的耗尽层中，并且用于提供与由掺杂的P / N结限定的波导配合的相干光源。掺杂的P / N结可以是双极晶体管的基极 - 集电极区域，并且被反向偏置，使得稀土离子提供相干光。

6. 发明授权

US06451672B1 Method for manufacturing electronic devices in semiconductor substrates provided with gettering sites 有权
标题翻译：制造具有吸杂位置的半导体衬底中的电子器件的方法
公开(公告)号：US06451672B1
公开(公告)日：2002-09-17
申请号：US09549889
申请日：2000-04-17
申请人： Davide Caruso , Vito Raineri , Mario Saggio , Umberto Stagnitti
发明人： Davide Caruso , Vito Raineri , Mario Saggio , Umberto Stagnitti
IPC分类号： H01L21322
CPC分类号： H01L21/3226 , H01L21/3223
摘要： This invention relates to a method for manufacturing electronic devices integrated monolithically in a semiconductor substrate delimited by two opposed front and back surfaces of a semiconductor material wafer. The method comprises at least a step of implanting ions of a noble gas, followed by a thermal treatment directed to form gettering microvoids in the semiconductor by evaporation of the gas. The ion implanting step is carried out through the back surface of the semiconductor wafer prior to starting the manufacturing process for the electronic devices, and also can be before the step of cleaning the front surface of the wafer.
摘要翻译：本发明涉及一种用于制造电子器件的方法，该电子器件整体地集成在由半导体材料晶片的两个相对的前表面和后表面限定的半导体衬底中。该方法至少包括注入稀有气体的离子的步骤，然后进行热处理，以通过蒸发气体在半导体中形成吸气微孔。在开始电子设备的制造过程之前，离子注入步骤通过半导体晶片的背面进行，并且还可以在清洁晶片的前表面的步骤之前。

7. 发明授权

US06433399B1 Infrared detector device of semiconductor material and manufacturing process thereof 有权
标题翻译：半导体材料红外探测器及其制造工艺
公开(公告)号：US06433399B1
公开(公告)日：2002-08-13
申请号：US09415022
申请日：1999-10-07
申请人： Albert Polman , Nicholas Hamelin , Peter Kik , Salvatore Coffa , Ferruccio Frisina , Mario Saggio
发明人： Albert Polman , Nicholas Hamelin , Peter Kik , Salvatore Coffa , Ferruccio Frisina , Mario Saggio
IPC分类号： H01L310232
CPC分类号： G02B6/12004 , H01L31/0352 , H01L31/103
摘要： An infrared detector device having a PN junction formed by a first semiconductor material region doped with rare earth ions and by a second semiconductor material region of opposite doping type. The detector device comprises a waveguide formed by a projecting structure extending on a substrate, including a reflecting layer and laterally delimited by a protection and containment oxide region. At least one portion of the waveguide is formed by the PN junction and has an end fed with light to be detected. The detector device has electrodes disposed laterally to and on the waveguide to enable efficient gathering of charge carriers generated by photoconversion.
摘要翻译：具有由掺杂有稀土离子的第一半导体材料区域和具有相反掺杂型的第二半导体材料区域形成的PN结的红外检测器装置。检测器装置包括由在衬底上延伸的突出结构形成的波导，包括反射层，并由保护和容纳氧化物区域横向界定。波导的至少一部分由PN结形成，并且具有馈送待检测光的端部。检测器装置具有横向设置在波导上的电极，以使得能够有效地收集通过光转换产生的电荷载流子。

8. 发明申请

US20060183267A1 Process for manufacturing a schottky contact on a semiconductor substrate 审中-公开
标题翻译：在半导体衬底上制造肖特基接触的工艺
公开(公告)号：US20060183267A1
公开(公告)日：2006-08-17
申请号：US11236304
申请日：2005-09-27
申请人： Fabrizio Roccaforte , Vito Raineri , Francesco La Via , Mario Saggio
发明人： Fabrizio Roccaforte , Vito Raineri , Francesco La Via , Mario Saggio
IPC分类号： H01L21/00
CPC分类号： H01L21/0435 , H01L21/0415
摘要： A process realizes a Schottky contact on an epitaxial layer of a semiconductor substrate. The process includes depositing a conductive metallic layer on a surface of the epitaxial layer, with achievement of a interface region of conductive metallic layer/semiconductor. The process further comprises a ionic irradiation step directed towards the surface of the epitaxial layer for forming a modified intermediate layer of at least one surface portion of the epitaxial layer for making the electric behavior of the interface region substantially dependant on the contact between the conductive metallic layer and the obtained modified intermediate layer.
摘要翻译：一种工艺在半导体衬底的外延层上实现肖特基接触。该方法包括在外延层的表面上沉积导电金属层，实现导电金属层/半导体的界面区域。该方法还包括指向外延层的表面的离子照射步骤，用于形成外延层的至少一个表面部分的改性中间层，以使界面区域的电性能基本上取决于导电金属层和得到的改性中间层。

9. 发明授权

US06762112B2 Method for manufacturing isolating structures 有权
标题翻译：隔离结构的制造方法
公开(公告)号：US06762112B2
公开(公告)日：2004-07-13
申请号：US10079925
申请日：2002-02-20
申请人： Vito Raineri , Mario Saggio
发明人： Vito Raineri , Mario Saggio
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/7602
摘要： A method for forming isolating structures in a silicon carbide layer includes depositing a masking layer on first and second portions of the silicon carbide layer, and forming openings through the masking layer to expose the first portions of the silicon carbide layer. Ions are implanted into the first portions of the silicon carbide layer. The silicon carbide layer is heated to form an oxide layer thereon having first portions on the first portions of the silicon carbide layer, and having second portions on the second portions of the silicon carbide layer. The first portions of the oxide layer are etched to form isolating regions in the silicon carbide layer.
摘要翻译：在碳化硅层中形成隔离结构的方法包括在碳化硅层的第一和第二部分上沉积掩模层，以及通过掩模层形成开口以露出碳化硅层的第一部分。离子被注入到碳化硅层的第一部分中。加热碳化硅层以形成其上具有在碳化硅层的第一部分上的第一部分并且在碳化硅层的第二部分上具有第二部分的氧化物层。蚀刻氧化物层的第一部分以在碳化硅层中形成隔离区。

10. 发明申请

US20080001223A1 Process for manufacturing a charge-balance power diode and an edge-termination structure for a charge-balance semiconductor power device 有权
标题翻译：用于制造电荷平衡功率二极管的工艺和用于电荷平衡半导体功率器件的边缘终端结构
公开(公告)号：US20080001223A1
公开(公告)日：2008-01-03
申请号：US11824169
申请日：2007-06-28
申请人： Mario Saggio , Domenico Murabito , Ferruccio Frisina
发明人： Mario Saggio , Domenico Murabito , Ferruccio Frisina
IPC分类号： H01L21/336 , H01L29/768
CPC分类号： H01L29/7811 , H01L21/324 , H01L29/0615 , H01L29/0634 , H01L29/0661 , H01L29/0692 , H01L29/0847 , H01L29/41766 , H01L29/66128 , H01L29/66727 , H01L29/66734 , H01L29/73 , H01L29/7396 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/8611 , H01L29/872
摘要： An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top surface and inside an active portion of the body; and forming an edge-termination structure. The edge-termination structure is formed by: a ring region having the first type of conductivity and a first doping level, set within a peripheral edge portion of the body and electrically connected to the active region; and a guard region, having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface and connecting the active region to the ring region. The process further envisages the steps of: forming a surface layer having the first type of conductivity on the first top surface, also at the peripheral edge portion, in contact with the guard region; and etching the surface layer in order to remove it above the edge portion in such a manner that the etch terminates inside the guard region.
摘要翻译：制造半导体功率器件的方法的一个实施例设想了以下步骤：提供由具有第一顶表面的半导体材料制成的本体; 在所述第一顶表面附近和所述主体的活动部分内部形成具有第一类型导电性的有源区; 并形成边缘终端结构。边缘终端结构通过以下方式形成：具有第一类型的导电性和第一掺杂水平的环形区域，其设置在主体的外围边缘部分内并电连接到有源区域; 以及保护区，其具有高于第一掺杂级的第一类型的导电性和第二掺杂级，设置在第一顶表面附近并将有源区连接到环区。该方法进一步设想了以下步骤：在第一顶表面上形成具有第一类型导电性的表面层，也在周边边缘部分形成与保护区域接触的表面层; 并且蚀刻表面层以便以这样的方式将其去除边缘部分，使得蚀刻终止于保护区域内。

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