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    • 4. 发明授权
    • Data processor having a plurality of operating units, logical registers,
and physical registers for parallel instructions execution
    • 数据处理器具有用于并行指令执行的多个操作单元,逻辑寄存器和物理寄存器
    • US4752873A
    • 1988-06-21
    • US865466
    • 1986-05-21
    • Tohru ShonaiEiki KamadaShigeo Takeuchi
    • Tohru ShonaiEiki KamadaShigeo Takeuchi
    • G06F9/38G06F15/31G06F12/00
    • G06F9/3889G06F9/3836G06F9/384G06F9/3885
    • In accordance with the invention, there are disposed a logical register group and a physical register group. Direct access is made to the logical register group on the basis of a register number designated by an instruction. To make access to the physical register group, there is disposed a circuit which converts the register number designated by the instruction to a physical register number.A plurality of arithmetical or logical operation units (ALUs) are disposed to execute a plurality of instructions in parallel. There is further disposed a circuit which supplies an operand data from the physical register group to each ALU and writes the operation result data of each ALU into the physical register group and into the logical register group.When a write register number designated by a preceding instruction A and a succeeding instruction B has the same value a, mutually different physical register numbers b' and b" are determined with respect to the write register number a for both instructions A and B. Therefore, the instruction B can be executed in parallel with the instruction A before the operation of the instruction A is complete.
    • 根据本发明,设置了逻辑寄存器组和物理寄存器组。 基于由指令指定的寄存器编号直接访问逻辑寄存器组。 为了访问物理寄存器组,设置了将由指令指定的寄存器号转换为物理寄存器号的电路。 多个算术逻辑运算单元(ALU)被设置成并行地执行多个指令。 另外设置有一个从物理寄存器组提供操作数据到每个ALU的电路,并将每个ALU的操作结果数据写入物理寄存器组并写入逻辑寄存器组。 当由前一条指令A和后续指令B指定的写入寄存器号码具有相同的值a时,相对于指令A和B两者的写入寄存器号a确定相互不同的物理寄存器编号b'和b“。 因此,在指令A的操作完成之前,可以与指令A并行地执行指令B.
    • 10. 发明授权
    • Data processor with multiple register queues
    • 具有多个寄存器队列的数据处理器
    • US6049839A
    • 2000-04-11
    • US172170
    • 1993-12-23
    • Hiroaki FujiiYasuhiro InagamiShigeo Takeuchi
    • Hiroaki FujiiYasuhiro InagamiShigeo Takeuchi
    • G06F9/34G06F9/30G06F9/38G06F13/00
    • G06F9/30134G06F9/384
    • A data processor includes a register group having registers of the number larger than the number of registers which can be designated by a register specifier field of an instruction. The register group consists of a plurality of register queues with respect to logical register numbers designated in the instruction, each register queue including a plurality of physical registers. In the data processor, a physical register number forming section is provided for converting the logical register number to a physical register number in the register queue corresponding to the logical register number, by using queue control information designated in the register specifier field and read/write information decided by the kind of the instruction and the position of the register specifier field in the instruction.
    • 数据处理器包括具有比可由指令的寄存器说明符字段指定的寄存器数量大的寄存器的寄存器组。 寄存器组包括相对于指令中指定的逻辑寄存器号的多个寄存器队列,每个寄存器队列包括多个物理寄存器。 在数据处理器中,提供物理寄存器号码形成部分,用于通过使用寄存器说​​明符字段中指定的队列控制信息和读取/写入将逻辑寄存器号码转换为对应于逻辑寄存器号码的寄存器队列中的物理寄存器号码 指令种类决定的信息和指令中寄存器说明符字段的位置。