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1. 发明授权

US5721865A Information processing apparatus with prefetch control for prefetching data structure from memory through cache memory 失效
标题翻译：具有预取控制的信息处理装置，用于通过高速缓冲存储器从存储器预取数据结构
公开(公告)号：US5721865A
公开(公告)日：1998-02-24
申请号：US588503
申请日：1996-01-18
申请人： Yooichi Shintani , Yoshikazu Tanaka , Naohiko Irie , William S. Worley, Jr. , B. Ramakrishna Rau , Rajiv Gupta , Frederic C. Amerson
发明人： Yooichi Shintani , Yoshikazu Tanaka , Naohiko Irie , William S. Worley, Jr. , B. Ramakrishna Rau , Rajiv Gupta , Frederic C. Amerson
IPC分类号： G06F9/345 , G06F9/38 , G06F12/02 , G06F12/08 , G06F17/16 , G06F9/34
CPC分类号： G06F9/3455 , G06F9/30047 , G06F9/30181 , G06F9/383 , G06F9/3834
摘要： To improve the function of a circuit for prefetching data accessed by a processor, a prefetch unit incorporates therein a circuit for issuing a request to read out one group of data to be prefetched and registers for holding the group of data read in response to the read request therein. The group of data are read out from a cache memory or a main memory under the control of a cache request unit. A plurality of groups of data can be prefetched. When data designation is made, the processor requests the cache memory to read a block to which the data to be prefetched belongs. A circuit is also included in the prefetch unit, wherein when prefetched data is subsequently updated by the processor, its updated data is made invalid. Elements of a vector complex in structure, such as an indexed vector or the like can be also read out. It is also possible to cope with an interrupt generated within the processor.
摘要翻译：为了改进用于预取由处理器访问的数据的电路的功能，预取单元在其中结合有用于发出读取需要预取的一组数据的请求的电路，并且用于保存响应于读取读取的数据组的寄存器请求。在高速缓存请求单元的控制下，从高速缓冲存储器或主存储器读出数据组。可以预取多组数据。当进行数据指定时，处理器请求高速缓冲存储器读取要预取的数据所属的块。预取单元中还包括一个电路，其中当处理器随后更新预取的数据时，其更新的数据变为无效。也可以读出结构中的向量复合体的元素，例如索引向量等。也可以处理处理器内产生的中断。

2. 发明授权

US4618926A Buffer storage control system 失效
标题翻译：缓冲存储控制系统
公开(公告)号：US4618926A
公开(公告)日：1986-10-21
申请号：US518698
申请日：1983-07-29
申请人： Kanji Kubo , Kenichi Wada , Yooichi Shintani
发明人： Kanji Kubo , Kenichi Wada , Yooichi Shintani
IPC分类号： G06F9/38 , G06F12/08 , G06F12/10 , G11C9/06
CPC分类号： G06F12/0846 , G06F12/0848
摘要： In a storage hierarchy system, a part of data stored in a main storage in held as a copy by a buffer storage of a smaller capacity and higher speed than the main storage. A processor fetches data from the buffer storage or stores data in the buffer storage at a high speed. A buffer storage control system includes a first buffer directory and a second buffer directory. The first buffer directory and the buffer storage are accessed by an address for a fetch request, while the second buffer directory and the buffer storage are accessed by an address for store request, whereby competition for the access to the buffer storage between the fetch and store operations is reduced.
摘要翻译：在存储分层系统中，存储在主存储器中的数据的一部分被保存为比主存储器更小容量和更高速度的缓冲存储器作为副本。处理器从缓冲存储器中取出数据或以高速将数据存储在缓冲存储器中。缓冲存储控制系统包括第一缓冲目录和第二缓冲目录。第一缓冲器目录和缓冲存储器由用于获取请求的地址访问，而第二缓冲器目录和缓冲存储器被存储请求的地址访问，由此在获取和存储之间访问缓冲存储器的竞争操作减少。

3. 发明授权

US4541047A Pipelined data processing system 失效
标题翻译：流水线数据处理系统
公开(公告)号：US4541047A
公开(公告)日：1985-09-10
申请号：US490166
申请日：1983-04-29
申请人： Kenichi Wada , Yooichi Shintani , Tsuguo Shimizu , Akira Yamaoka
发明人： Kenichi Wada , Yooichi Shintani , Tsuguo Shimizu , Akira Yamaoka
IPC分类号： G06F9/38 , G06F9/48
CPC分类号： G06F9/3863
摘要： A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit for operating all instructions to be executed by the data processing unit, a first group of general purpose registers for storing the operation results of the main operation unit, a pre-operation unit for operating a portion of instructions which frequently appear and which can be operated with a small number of circuit components, a second group of general purpose registers for storing the operation results of the pre-operation unit, and control means for storing the operation result of the pre-operation unit into the second general purpose register at least one operation stage earlier than the storing of the operation result of the main operation unit into the first general purpose register and storing the contents of the second general purpose registers into the first general purpose registers when an interruption occurs.
摘要翻译：一种用于在流水线模式中执行多级的指令的数据处理系统包括用于操作由数据处理单元执行的所有指令的主操作单元，用于存储主程序的操作结果的第一组通用寄存器操作单元，用于操作经常出现并且可以用少量电路组件操作的指令的一部分的预操作单元，用于存储预操作单元的操作结果的第二组通用寄存器，以及控制装置，用于将预操作单元的操作结果存储在第二通用寄存器中，比将主操作单元的操作结果存储到第一通用寄存器中的至少一个操作阶段存储第二通用寄存器的内容当发生中断时，通用寄存器进入第一个通用寄存器。

4. 发明授权

US5842207A Method for storing records of a distributed database by plural processors to provide a host processor with sorted records belonging to one of a plurality of key sections 失效
标题翻译：用于存储由多个处理器分配的数据库的记录以向主机处理器提供归属于多个关键部分中的一个的排序记录的方法
公开(公告)号：US5842207A
公开(公告)日：1998-11-24
申请号：US911617
申请日：1992-07-10
申请人： Shinji Fujiwara , Yooichi Shintani , Mitsuru Nagasaka , Naoki Hamanaka , Mikiko Suzuki
发明人： Shinji Fujiwara , Yooichi Shintani , Mitsuru Nagasaka , Naoki Hamanaka , Mikiko Suzuki
IPC分类号： G06F7/24 , G06F17/30
CPC分类号： G06F7/24 , Y10S707/99937
摘要： A sorting method used with a distributed database having a plurality of first processors for holding partial records of a database that is divided into a plurality of portions and a host processor for accessing to each of the first processors. The method comprises the steps of: assigning a plurality of sections into which the distribution range of key values of records of the database is partitioned to a plurality of second processors in the first processors, and information for representing storage positions of the records to the second processors to which the sections of the key values, to which the records belong, are assigned; and sorting the plurality of key values, which have been received, in the second processors to produce key tables in which the information for representing the storage positions of the records which has been received is registrated together with the sorted key values, as the sorting result.
摘要翻译：一种与分布式数据库一起使用的排序方法，所述分布式数据库具有多个第一处理器，用于保存被划分成多个部分的数据库的部分记录以及用于访问每个第一处理器的主机处理器。该方法包括以下步骤：将数据库的记录的键值的分配范围分配到多个第一处理器中的多个第二处理器的多个区段，以及用于将记录的存储位置表示到第二处理区域的信息分配了记录所属键值的部分的处理器; 并且将已经接收到的多个密钥值排序在第二处理器中以产生密钥表，其中用于表示已经接收的记录的存储位置的信息与排序的关键字一起被登记在一起作为排序结果。

5. 发明授权

US5671382A Information processing system and information processing method for executing instructions in parallel 失效
标题翻译：用于并行执行指令的信息处理系统和信息处理方法
公开(公告)号：US5671382A
公开(公告)日：1997-09-23
申请号：US915204
申请日：1992-04-20
申请人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
发明人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/3836 , G06F9/3842 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F9/3885
摘要： An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.
摘要翻译：一种信息处理设备，其中概念地逐个处理指令，并且其结果在概念上有序地写入存储器包括能够并行地解码M个指令和读取操作数的指令控制电路，N（N> / = M）个执行电路能够执行并行执行多个指令的检测电路，用于确定由指令控制电路解码的M个指令所需的N个执行电路的所有M个执行电路是否为空的检测电路，以及用于保留执行的备用电路的M解码指令，而检测不能检测到足够的空位。

6. 发明授权

US4942525A Data processor for concurrent executing of instructions by plural execution units 失效
标题翻译：用于由多个执行单元并发执行指令的数据处理器
公开(公告)号：US4942525A
公开(公告)日：1990-07-17
申请号：US123139
申请日：1987-11-20
申请人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
发明人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/3836 , G06F9/3842 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F9/3885
摘要： An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.
摘要翻译：一种信息处理设备，其中概念地逐个处理指令，并且其结果在概念上有序地写入存储器包括能够并行地解码M个指令和读取操作数的指令控制电路，N（N> / = M）个执行电路能够执行并行执行多个指令的检测电路，用于确定由指令控制电路解码的M个指令所需的N个执行电路的所有M个执行电路是否为空的检测电路，以及用于保留执行的备用电路的M解码指令，而检测不能检测到足够的空位。

7. 发明授权

US4831515A Information processing apparatus for determining sequence of parallel executing instructions in response to storage requirements thereof 失效
标题翻译：用于根据其存储要求确定并行执行指令的顺序的信息处理装置
公开(公告)号：US4831515A
公开(公告)日：1989-05-16
申请号：US827603
申请日：1986-02-10
申请人： Eiki Kamada , Yooichi Shintani , Tohru Shonai , Shigeo Takeuchi
发明人： Eiki Kamada , Yooichi Shintani , Tohru Shonai , Shigeo Takeuchi
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/3824
摘要： An information processing apparatus for executing instructions in parallel includes circuitry which, when a first instruction requesting reading of an operand from a certain address of the main storage or buffer storage has been decoded, detects among instructions in execution the presence of a second instruction requesting writing of an operand held by a register such as a general-purpose register into that address of the main storage without implementing an operation on the operand. If the second instruction has been detected, the invention reads out an operand from the register specified for operand reading by said second instruction before operand writing into the main storage by the second instruction is completed.
摘要翻译：一种用于并行执行指令的信息处理装置，包括当从主存储器或缓冲存储器的特定地址读取操作数的第一指令被解码时，在执行指令之间检测存在请求写入的第二指令的电路由通用寄存器等寄存器保存在主存储器的地址中，而不对操作数进行操作。如果已经检测到第二指令，则本发明在通过第二指令完成对操作数写入主存储器的操作数之前，从由所述第二指令指定的用于操作数读取的寄存器中读出操作数。

8. 发明授权

US5922068A Information processing system and information processing method for executing instructions in parallel 失效
标题翻译：用于并行执行指令的信息处理系统和信息处理方法
公开(公告)号：US5922068A
公开(公告)日：1999-07-13
申请号：US888645
申请日：1997-07-07
申请人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
发明人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/3836 , G06F9/3842 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F9/3885
摘要： An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.
摘要翻译：一种信息处理设备，其中概念地逐个处理指令，并且其结果在概念上有序地写入存储器包括能够并行地解码M个指令和读取操作数的指令控制电路，N（N> / = M）个执行电路能够执行并行执行多个指令的检测电路，用于确定由指令控制电路解码的M个指令所需的N个执行电路的所有M个执行电路是否为空的检测电路，以及用于保留执行的备用电路的M解码指令，而检测不能检测到足够的空位。

9. 发明授权

US5515531A Parallel database processing system and retrieval method using secondary key 失效
标题翻译：并行数据库处理系统和使用次级密钥的检索方法
公开(公告)号：US5515531A
公开(公告)日：1996-05-07
申请号：US69193
申请日：1993-05-28
申请人： Shinji Fujiwara , Mitsuru Nagasaka , Yooichi Shintani
发明人： Shinji Fujiwara , Mitsuru Nagasaka , Yooichi Shintani
IPC分类号： G06F12/00 , G06F17/30
CPC分类号： G06F17/30321 , G06F17/30433 , Y10S707/99933
摘要： A parallel database processing system a global database processing unit, a plurality of local database processing units, and a network interconnecting the global database processing unit and a plurality of local database processing units, wherein one table containing a number of records is partitioned into local tables, each local table being provided in a corresponding one of the local database processing units, secondary key indexes representing correspondence between the values of secondary keys for all records in the table and access information to the records corresponding to the secondary keys, are partitioned on the basis of the values into local secondary key indexes, each set of the local secondary key indexes being provided in a corresponding one of the local database processing units, and an identifying unit is provided in the global database processing unit, the identifying unit responsive to a retrieval request with the secondary key identifying the local database processing unit having the local secondary key index corresponding to the secondary key. At the global database processing unit, the retrieval request with the secondary key is received, the identifying unit identifies the local database processing unit having the local secondary key index corresponding to the secondary key, and the retrieval request with the secondary key is transferred to the identified local database processing unit. At the identified local database processing unit, its own local secondary key indexes are referred to obtain access information corresponding to the transferred retrieval request with the secondary key, and the retrieval request with the secondary key is processed by using the access information so that the local table corresponding to the retrieval request with the secondary key is accessed.
摘要翻译：并行数据库处理系统，全局数据库处理单元，多个本地数据库处理单元，以及互连全球数据库处理单元和多个本地数据库处理单元的网络，其中包含多个记录的一个表被划分为本地表每个本地表被提供在本地数据库处理单元中的对应的一个中，表示对于表中的所有记录的辅助键的值之间的对应关系的次要密钥索引以及对应于次要密钥的记录的访问信息被划分在将所述值作为本地二次密钥索引的基础，在本地数据库处理单元中相应的一个本地数据库处理单元中提供每组本地辅助密钥索引，并且在全局数据库处理单元中提供识别单元，所述识别单元响应于检索请求与辅助键标识本地数据库进程具有对应于次要密钥的本地次要密钥索引的单元。在全局数据库处理单元处，接收到具有辅助密钥的检索请求，识别单元识别具有与次密钥对应的本地次要密钥索引的本地数据库处理单元，并且将具有辅助密钥的检索请求传送到识别本地数据库处理单元。在所识别的本地数据库处理单元，其自身的本地次要密钥索引被引用以获得与所传送的检索请求相对应的与辅助密钥相关的访问信息，并且通过使用访问信息来处理具有辅助密钥的检索请求，使得本地访问与辅助密钥的检索请求对应的表。

10. 发明授权

US4928226A Data processor for parallelly executing conflicting instructions 失效
标题翻译：用于并行执行冲突指令的数据处理器
公开(公告)号：US4928226A
公开(公告)日：1990-05-22
申请号：US124839
申请日：1987-11-24
申请人： Eiki Kamada , Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Kiyoshi Inoue
发明人： Eiki Kamada , Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3836
摘要： A data processor includes an instruction detection unit for detecting that a succeeding instruction writes a read-out operand into a general register group without subjecting it to arithmetic or logical operation, in accordance with instruction decode informations provided by an instruction hold unit; a conflict detection unit for detecting a conflicting state that the preceding instruction performs a write operation into a general register of the general register group and the succeeding instruction reads an operand from the same general register, in accordance with instruction decode informations provided by the instruction hold unit; and a contention detection unit for detecting a contention state that the preceding instruction performs a write operation into the same general register and the succeeding instruction also performs a write operation into the same general register, in accordance with instruction decode informations provided by the instruction hold unit.
摘要翻译：数据处理器包括：指令检测单元，用于根据由指令保持单元提供的指令解码信息，检测后续指令将读出操作数写入通用寄存器组，而不对其进行算术或逻辑运算; 冲突检测单元，用于检测前一指令对通用寄存器组的通用寄存器执行写入操作的冲突状态，并且后续指令根据由指令保持提供的指令解码信息从同一通用寄存器读取操作数单元; 以及竞争检测单元，用于根据由指令保持单元提供的指令解码信息，检测前一指令对同一通用寄存器执行写操作的竞争状态，并且后续指令也对同一通用寄存器执行写操作。

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