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1. 发明授权

US4831515A Information processing apparatus for determining sequence of parallel executing instructions in response to storage requirements thereof 失效
标题翻译：用于根据其存储要求确定并行执行指令的顺序的信息处理装置
公开(公告)号：US4831515A
公开(公告)日：1989-05-16
申请号：US827603
申请日：1986-02-10
申请人： Eiki Kamada , Yooichi Shintani , Tohru Shonai , Shigeo Takeuchi
发明人： Eiki Kamada , Yooichi Shintani , Tohru Shonai , Shigeo Takeuchi
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/3824
摘要： An information processing apparatus for executing instructions in parallel includes circuitry which, when a first instruction requesting reading of an operand from a certain address of the main storage or buffer storage has been decoded, detects among instructions in execution the presence of a second instruction requesting writing of an operand held by a register such as a general-purpose register into that address of the main storage without implementing an operation on the operand. If the second instruction has been detected, the invention reads out an operand from the register specified for operand reading by said second instruction before operand writing into the main storage by the second instruction is completed.
摘要翻译：一种用于并行执行指令的信息处理装置，包括当从主存储器或缓冲存储器的特定地址读取操作数的第一指令被解码时，在执行指令之间检测存在请求写入的第二指令的电路由通用寄存器等寄存器保存在主存储器的地址中，而不对操作数进行操作。如果已经检测到第二指令，则本发明在通过第二指令完成对操作数写入主存储器的操作数之前，从由所述第二指令指定的用于操作数读取的寄存器中读出操作数。

2. 发明授权

US4760520A Data processor capable of executing instructions under prediction 失效
标题翻译：能够执行预测指令的数据处理器
公开(公告)号：US4760520A
公开(公告)日：1988-07-26
申请号：US793545
申请日：1985-10-31
申请人： Yooichi Shintani , Tohru Shonai , Eiki Kamada , Shigeo Takeuchi
发明人： Yooichi Shintani , Tohru Shonai , Eiki Kamada , Shigeo Takeuchi
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3889 , G06F9/3842
摘要： A buffer or a plurality of buffers are provided each for holding a write address and an address specifying a write position which are obtained as a result of an execution based on a predicted result. The execution of the instruction is continued up to the operation stage regadless of whether or not the instruction is being executed in the predicted state, the data and the write address are held in the buffer written. The data in the buffer is canceled if the prediction is found to be wrong when the predicted state is completed, and the data is utilized if the prediction is found to be correct.
摘要翻译：提供缓冲器或多个缓冲器，每个缓冲器用于保持写入地址和指定作为基于预测结果的执行结果而获得的写入位置的地址。指令的执行继续到操作阶段，无论在预测状态下是否执行指令，数据和写入地址都被保存在写入的缓冲器中。如果在预测状态完成时发现预测错误，则缓冲器中的数据被取消，并且如果发现该预测是正确的，则利用该数据。

3. 发明授权

US5671382A Information processing system and information processing method for executing instructions in parallel 失效
标题翻译：用于并行执行指令的信息处理系统和信息处理方法
公开(公告)号：US5671382A
公开(公告)日：1997-09-23
申请号：US915204
申请日：1992-04-20
申请人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
发明人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/3836 , G06F9/3842 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F9/3885
摘要： An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.
摘要翻译：一种信息处理设备，其中概念地逐个处理指令，并且其结果在概念上有序地写入存储器包括能够并行地解码M个指令和读取操作数的指令控制电路，N（N> / = M）个执行电路能够执行并行执行多个指令的检测电路，用于确定由指令控制电路解码的M个指令所需的N个执行电路的所有M个执行电路是否为空的检测电路，以及用于保留执行的备用电路的M解码指令，而检测不能检测到足够的空位。

4. 发明授权

US4942525A Data processor for concurrent executing of instructions by plural execution units 失效
标题翻译：用于由多个执行单元并发执行指令的数据处理器
公开(公告)号：US4942525A
公开(公告)日：1990-07-17
申请号：US123139
申请日：1987-11-20
申请人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
发明人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/3836 , G06F9/3842 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F9/3885
摘要： An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.
摘要翻译：一种信息处理设备，其中概念地逐个处理指令，并且其结果在概念上有序地写入存储器包括能够并行地解码M个指令和读取操作数的指令控制电路，N（N> / = M）个执行电路能够执行并行执行多个指令的检测电路，用于确定由指令控制电路解码的M个指令所需的N个执行电路的所有M个执行电路是否为空的检测电路，以及用于保留执行的备用电路的M解码指令，而检测不能检测到足够的空位。

5. 发明授权

US5075849A Information processor providing enhanced handling of address-conflicting instructions during pipeline processing 失效
标题翻译：信息处理者在管道加工期间提供地址冲突指令的增强处理
公开(公告)号：US5075849A
公开(公告)日：1991-12-24
申请号：US292346
申请日：1988-12-30
申请人： Kazunori Kuriyama , Yooichi Shintani , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
发明人： Kazunori Kuriyama , Yooichi Shintani , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3824
摘要： An information processor detects a conflict between successive instructions by determining whether a preceding instruction under execution calls for fetching a first operand from a main memory, generating execution result data based on the first operand and updating one of a plurality of address data designated by a to-be-executed succeeding instruction, with the execution result data. When a conflict is detected, there is supplied to an address adder at least some of the plurality of address data determined by a type of the preceding instruction to complete an operand address calculation stage for the succeeding instruction. Then, before the one address data is updated by the preceding instruction after the first operand has been fetched from the main memory in an operand fetch stage for the preceding instruction, an operation determined by the preceding instruction is performed on the output of the address adder and the fetched first operand to generate an address equal to a sum of the plurality of address data, excluding said one address, and the execution result data for the preceding instruction, and this address is used as the address of the second operand of the succeeding instruction.
摘要翻译：信息处理器通过确定执行中的前一指令是否从主存储器取出第一操作数，检测基于第一操作数的执行结果数据，并更新由a至执行后续指令，执行结果数据。当检测到冲突时，由地址加法器提供由前一条指令的类型确定的多个地址数据中的至少一些，以完成后续指令的操作数地址计算阶段。然后，在前一条指令的操作数获取级中从主存储器取出第一操作数之前，先前指令更新一个地址数据之前，对地址加法器的输出执行由先前指令确定的操作以及所取出的第一操作数，以产生等于除所述一个地址之外的多个地址数据之和的地址和前一条指令的执行结果数据，并且该地址被用作后续的第二操作数的地址指令。

6. 发明授权

US5922068A Information processing system and information processing method for executing instructions in parallel 失效
标题翻译：用于并行执行指令的信息处理系统和信息处理方法
公开(公告)号：US5922068A
公开(公告)日：1999-07-13
申请号：US888645
申请日：1997-07-07
申请人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
发明人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/3836 , G06F9/3842 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F9/3885
摘要： An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.
摘要翻译：一种信息处理设备，其中概念地逐个处理指令，并且其结果在概念上有序地写入存储器包括能够并行地解码M个指令和读取操作数的指令控制电路，N（N> / = M）个执行电路能够执行并行执行多个指令的检测电路，用于确定由指令控制电路解码的M个指令所需的N个执行电路的所有M个执行电路是否为空的检测电路，以及用于保留执行的备用电路的M解码指令，而检测不能检测到足够的空位。

7. 发明授权

US4928226A Data processor for parallelly executing conflicting instructions 失效
标题翻译：用于并行执行冲突指令的数据处理器
公开(公告)号：US4928226A
公开(公告)日：1990-05-22
申请号：US124839
申请日：1987-11-24
申请人： Eiki Kamada , Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Kiyoshi Inoue
发明人： Eiki Kamada , Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3836
摘要： A data processor includes an instruction detection unit for detecting that a succeeding instruction writes a read-out operand into a general register group without subjecting it to arithmetic or logical operation, in accordance with instruction decode informations provided by an instruction hold unit; a conflict detection unit for detecting a conflicting state that the preceding instruction performs a write operation into a general register of the general register group and the succeeding instruction reads an operand from the same general register, in accordance with instruction decode informations provided by the instruction hold unit; and a contention detection unit for detecting a contention state that the preceding instruction performs a write operation into the same general register and the succeeding instruction also performs a write operation into the same general register, in accordance with instruction decode informations provided by the instruction hold unit.
摘要翻译：数据处理器包括：指令检测单元，用于根据由指令保持单元提供的指令解码信息，检测后续指令将读出操作数写入通用寄存器组，而不对其进行算术或逻辑运算; 冲突检测单元，用于检测前一指令对通用寄存器组的通用寄存器执行写入操作的冲突状态，并且后续指令根据由指令保持提供的指令解码信息从同一通用寄存器读取操作数单元; 以及竞争检测单元，用于根据由指令保持单元提供的指令解码信息，检测前一指令对同一通用寄存器执行写操作的竞争状态，并且后续指令也对同一通用寄存器执行写操作。

8. 发明授权

US4858105A Pipelined data processor capable of decoding and executing plural instructions in parallel 失效
标题翻译：能够并行地解码和执行多个指令的流水线数据处理器
公开(公告)号：US4858105A
公开(公告)日：1989-08-15
申请号：US30434
申请日：1987-03-26
申请人： Kazunori Kuriyama , Yooichi Shintani , Akira Yamaoka , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
发明人： Kazunori Kuriyama , Yooichi Shintani , Akira Yamaoka , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3816 , G06F9/30149 , G06F9/3822 , G06F9/3836 , G06F9/3889
摘要： A pipelined data processor comprises a circuit for storing two instructions in a pair of instruction registers, a circuit for detecting whether those instructions are a combination of an instruction requesting the use of an operation unit and an instruction requesting the use of another resource, and a circuit to control the execution of the instructions when the decision of the detection circuit is affirmative such that those instructions are executed by the operation unit and the resource in a plurality of stages.
摘要翻译：流水线数据处理器包括用于在一对指令寄存器中存储两个指令的电路，用于检测这些指令是否是请求使用操作单元的指令与请求使用另一资源的指令的组合的电路，以及电路，用于当检测电路的判定为肯定时控制指令的执行，使得这些指令由操作单元和资源在多个级中执行。

9. 发明授权

US4752873A Data processor having a plurality of operating units, logical registers, and physical registers for parallel instructions execution 失效
标题翻译：数据处理器具有用于并行指令执行的多个操作单元，逻辑寄存器和物理寄存器
公开(公告)号：US4752873A
公开(公告)日：1988-06-21
申请号：US865466
申请日：1986-05-21
申请人： Tohru Shonai , Eiki Kamada , Shigeo Takeuchi
发明人： Tohru Shonai , Eiki Kamada , Shigeo Takeuchi
IPC分类号： G06F9/38 , G06F15/31 , G06F12/00
CPC分类号： G06F9/3889 , G06F9/3836 , G06F9/384 , G06F9/3885
摘要： In accordance with the invention, there are disposed a logical register group and a physical register group. Direct access is made to the logical register group on the basis of a register number designated by an instruction. To make access to the physical register group, there is disposed a circuit which converts the register number designated by the instruction to a physical register number.A plurality of arithmetical or logical operation units (ALUs) are disposed to execute a plurality of instructions in parallel. There is further disposed a circuit which supplies an operand data from the physical register group to each ALU and writes the operation result data of each ALU into the physical register group and into the logical register group.When a write register number designated by a preceding instruction A and a succeeding instruction B has the same value a, mutually different physical register numbers b' and b" are determined with respect to the write register number a for both instructions A and B. Therefore, the instruction B can be executed in parallel with the instruction A before the operation of the instruction A is complete.
摘要翻译：根据本发明，设置了逻辑寄存器组和物理寄存器组。基于由指令指定的寄存器编号直接访问逻辑寄存器组。为了访问物理寄存器组，设置了将由指令指定的寄存器号转换为物理寄存器号的电路。多个算术逻辑运算单元（ALU）被设置成并行地执行多个指令。另外设置有一个从物理寄存器组提供操作数据到每个ALU的电路，并将每个ALU的操作结果数据写入物理寄存器组并写入逻辑寄存器组。当由前一条指令A和后续指令B指定的写入寄存器号码具有相同的值a时，相对于指令A和B两者的写入寄存器号a确定相互不同的物理寄存器编号b'和b“。因此，在指令A的操作完成之前，可以与指令A并行地执行指令B.

10. 发明授权

US5845321A Store buffer apparatus with two store buffers to increase throughput of a store operation 失效
标题翻译：具有两个存储缓冲器的存储缓冲装置，以增加存储操作的吞吐量
公开(公告)号：US5845321A
公开(公告)日：1998-12-01
申请号：US729837
申请日：1996-10-15
申请人： Motohisa Ito , Eiki Kamada , Toshiko Isobe , Kei Yamamoto , Katsutoshi Uehara
发明人： Motohisa Ito , Eiki Kamada , Toshiko Isobe , Kei Yamamoto , Katsutoshi Uehara
IPC分类号： G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0855
摘要： A store buffer apparatus connected to a CPU and a main storage unit includes a first buffer for holding a pair of store address and store data in the main storage unit supplied from an operation execution unit of the CPU, a first latch connected to the first buffer means for holding the store address, a second latch connected to the first latch for holding an output of the first latch, a judgment device for comparing an output read out from the address array with an output of the second latch to thereby judge whether the cache hit check for the store address is successful or not and a second buffer for holding the pair of store data and store address having successful cache hit check judged by the judgment device. Occurrence of the state that the store buffer is full is reduced. Two data stored in the second buffer can possess a format into which the two data can be merged.
摘要翻译：连接到CPU和主存储单元的存储缓冲装置包括：第一缓冲器，用于保持一对存储地址并将数据存储在从CPU的操作执行单元提供的主存储单元中;第一锁存器，连接到第一缓冲器用于保存存储地址的装置，连接到第一锁存器的第二锁存器，用于保持第一锁存器的输出;判断装置，用于将从地址阵列读出的输出与第二锁存器的输出进行比较，从而判断高速缓存命中检查存储地址是否成功，以及第二缓冲器，用于保持由判断装置判断的具有成功的高速缓存命中检查的一对存储数据和存储地址。存储缓冲区已满的状态的发生被减少。存储在第二缓冲器中的两个数据可以具有可以合并两个数据的格式。

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