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1. 发明授权

US5671382A Information processing system and information processing method for executing instructions in parallel 失效
标题翻译：用于并行执行指令的信息处理系统和信息处理方法
公开(公告)号：US5671382A
公开(公告)日：1997-09-23
申请号：US915204
申请日：1992-04-20
申请人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
发明人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/3836 , G06F9/3842 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F9/3885
摘要： An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.
摘要翻译：一种信息处理设备，其中概念地逐个处理指令，并且其结果在概念上有序地写入存储器包括能够并行地解码M个指令和读取操作数的指令控制电路，N（N> / = M）个执行电路能够执行并行执行多个指令的检测电路，用于确定由指令控制电路解码的M个指令所需的N个执行电路的所有M个执行电路是否为空的检测电路，以及用于保留执行的备用电路的M解码指令，而检测不能检测到足够的空位。

2. 发明授权

US4942525A Data processor for concurrent executing of instructions by plural execution units 失效
标题翻译：用于由多个执行单元并发执行指令的数据处理器
公开(公告)号：US4942525A
公开(公告)日：1990-07-17
申请号：US123139
申请日：1987-11-20
申请人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
发明人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/3836 , G06F9/3842 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F9/3885
摘要： An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.
摘要翻译：一种信息处理设备，其中概念地逐个处理指令，并且其结果在概念上有序地写入存储器包括能够并行地解码M个指令和读取操作数的指令控制电路，N（N> / = M）个执行电路能够执行并行执行多个指令的检测电路，用于确定由指令控制电路解码的M个指令所需的N个执行电路的所有M个执行电路是否为空的检测电路，以及用于保留执行的备用电路的M解码指令，而检测不能检测到足够的空位。

3. 发明授权

US5075849A Information processor providing enhanced handling of address-conflicting instructions during pipeline processing 失效
标题翻译：信息处理者在管道加工期间提供地址冲突指令的增强处理
公开(公告)号：US5075849A
公开(公告)日：1991-12-24
申请号：US292346
申请日：1988-12-30
申请人： Kazunori Kuriyama , Yooichi Shintani , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
发明人： Kazunori Kuriyama , Yooichi Shintani , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3824
摘要： An information processor detects a conflict between successive instructions by determining whether a preceding instruction under execution calls for fetching a first operand from a main memory, generating execution result data based on the first operand and updating one of a plurality of address data designated by a to-be-executed succeeding instruction, with the execution result data. When a conflict is detected, there is supplied to an address adder at least some of the plurality of address data determined by a type of the preceding instruction to complete an operand address calculation stage for the succeeding instruction. Then, before the one address data is updated by the preceding instruction after the first operand has been fetched from the main memory in an operand fetch stage for the preceding instruction, an operation determined by the preceding instruction is performed on the output of the address adder and the fetched first operand to generate an address equal to a sum of the plurality of address data, excluding said one address, and the execution result data for the preceding instruction, and this address is used as the address of the second operand of the succeeding instruction.
摘要翻译：信息处理器通过确定执行中的前一指令是否从主存储器取出第一操作数，检测基于第一操作数的执行结果数据，并更新由a至执行后续指令，执行结果数据。当检测到冲突时，由地址加法器提供由前一条指令的类型确定的多个地址数据中的至少一些，以完成后续指令的操作数地址计算阶段。然后，在前一条指令的操作数获取级中从主存储器取出第一操作数之前，先前指令更新一个地址数据之前，对地址加法器的输出执行由先前指令确定的操作以及所取出的第一操作数，以产生等于除所述一个地址之外的多个地址数据之和的地址和前一条指令的执行结果数据，并且该地址被用作后续的第二操作数的地址指令。

4. 发明授权

US5922068A Information processing system and information processing method for executing instructions in parallel 失效
标题翻译：用于并行执行指令的信息处理系统和信息处理方法
公开(公告)号：US5922068A
公开(公告)日：1999-07-13
申请号：US888645
申请日：1997-07-07
申请人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
发明人： Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/3836 , G06F9/3842 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F9/3885
摘要： An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.
摘要翻译：一种信息处理设备，其中概念地逐个处理指令，并且其结果在概念上有序地写入存储器包括能够并行地解码M个指令和读取操作数的指令控制电路，N（N> / = M）个执行电路能够执行并行执行多个指令的检测电路，用于确定由指令控制电路解码的M个指令所需的N个执行电路的所有M个执行电路是否为空的检测电路，以及用于保留执行的备用电路的M解码指令，而检测不能检测到足够的空位。

5. 发明授权

US4928226A Data processor for parallelly executing conflicting instructions 失效
标题翻译：用于并行执行冲突指令的数据处理器
公开(公告)号：US4928226A
公开(公告)日：1990-05-22
申请号：US124839
申请日：1987-11-24
申请人： Eiki Kamada , Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Kiyoshi Inoue
发明人： Eiki Kamada , Yooichi Shintani , Kazunori Kuriyama , Tohru Shonai , Kiyoshi Inoue
IPC分类号： G06F9/38
CPC分类号： G06F9/3836
摘要： A data processor includes an instruction detection unit for detecting that a succeeding instruction writes a read-out operand into a general register group without subjecting it to arithmetic or logical operation, in accordance with instruction decode informations provided by an instruction hold unit; a conflict detection unit for detecting a conflicting state that the preceding instruction performs a write operation into a general register of the general register group and the succeeding instruction reads an operand from the same general register, in accordance with instruction decode informations provided by the instruction hold unit; and a contention detection unit for detecting a contention state that the preceding instruction performs a write operation into the same general register and the succeeding instruction also performs a write operation into the same general register, in accordance with instruction decode informations provided by the instruction hold unit.
摘要翻译：数据处理器包括：指令检测单元，用于根据由指令保持单元提供的指令解码信息，检测后续指令将读出操作数写入通用寄存器组，而不对其进行算术或逻辑运算; 冲突检测单元，用于检测前一指令对通用寄存器组的通用寄存器执行写入操作的冲突状态，并且后续指令根据由指令保持提供的指令解码信息从同一通用寄存器读取操作数单元; 以及竞争检测单元，用于根据由指令保持单元提供的指令解码信息，检测前一指令对同一通用寄存器执行写操作的竞争状态，并且后续指令也对同一通用寄存器执行写操作。

6. 发明授权

US4858105A Pipelined data processor capable of decoding and executing plural instructions in parallel 失效
标题翻译：能够并行地解码和执行多个指令的流水线数据处理器
公开(公告)号：US4858105A
公开(公告)日：1989-08-15
申请号：US30434
申请日：1987-03-26
申请人： Kazunori Kuriyama , Yooichi Shintani , Akira Yamaoka , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
发明人： Kazunori Kuriyama , Yooichi Shintani , Akira Yamaoka , Tohru Shonai , Eiki Kamada , Kiyoshi Inoue
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3816 , G06F9/30149 , G06F9/3822 , G06F9/3836 , G06F9/3889
摘要： A pipelined data processor comprises a circuit for storing two instructions in a pair of instruction registers, a circuit for detecting whether those instructions are a combination of an instruction requesting the use of an operation unit and an instruction requesting the use of another resource, and a circuit to control the execution of the instructions when the decision of the detection circuit is affirmative such that those instructions are executed by the operation unit and the resource in a plurality of stages.
摘要翻译：流水线数据处理器包括用于在一对指令寄存器中存储两个指令的电路，用于检测这些指令是否是请求使用操作单元的指令与请求使用另一资源的指令的组合的电路，以及电路，用于当检测电路的判定为肯定时控制指令的执行，使得这些指令由操作单元和资源在多个级中执行。

7. 发明授权

US4916606A Pipelined parallel data processing apparatus for directly transferring operand data between preceding and succeeding instructions 失效
标题翻译：用于在先前和后续指令之间直接传送操作数数据的流水线并行数据处理装置
公开(公告)号：US4916606A
公开(公告)日：1990-04-10
申请号：US75528
申请日：1987-07-20
申请人： Akira Yamaoka , Kenichi Wada , Kazunori Kuriyama , Yooichi Shintani
发明人： Akira Yamaoka , Kenichi Wada , Kazunori Kuriyama , Yooichi Shintani
IPC分类号： G06F9/38
CPC分类号： G06F9/3889 , G06F9/3824
摘要： A data processing apparatus of processing first instruction of a type in which the result of operation of the first instruction is stored in at least one storage location designated by operands of the first instruction and second instruction of a type which succeeds to the first instruction and makes use of the result of operation of the first instruction as operand data. The apparatus comprises an OSC control circuit for detecting whether at least a part of the result of operation of the first instruction is to be used or not as the operand data for the second instruction, and an arithmetic unit for allowing the result of operation of the first instruction to be directly used as the operand data for the second instruction when the OSC control circuit detects the given condition is fulfilled.
摘要翻译：一种处理第一指令的第一指令的数据处理装置，其中第一指令的操作结果被存储在由第一指令的操作数指定的至少一个存储位置中，并且第二指令成为第一指令成功的类型使用第一条指令的操作结果作为操作数据。该装置包括用于检测是否要使用第一指令的操作结果的至少一部分作为第二指令的操作数数据的OSC控制电路，以及用于允许第二指令的操作结果的运算单元当OSC控制电路检测到给定条件时，直接用作第二指令的操作数数据的第一指令被满足。

8. 发明授权

US5706465A Computers having cache memory 失效
标题翻译：具有高速缓冲存储器的计算机
公开(公告)号：US5706465A
公开(公告)日：1998-01-06
申请号：US215109
申请日：1994-03-21
申请人： Hiroshi Kurokawa , Kazunori Kuriyama , Naohiko Irie
发明人： Hiroshi Kurokawa , Kazunori Kuriyama , Naohiko Irie
IPC分类号： G06F9/38 , G06F12/00 , G06F12/08 , G06F13/00
CPC分类号： G06F9/3877 , G06F12/0888 , G06F9/3824
摘要： An auxiliary data processor having an built-in multi-entry data memory is directly connected to a main storage, and executes, directly accessing the main storage, commands sent from a plurality of instruction processors. One data memory entry is assigned to an instruction processor that issued a command, and reserves data fetched from the main storage in response to the command so that the next command can use part of that data. A tag circuit holds an identifier of each instruction processor to which a data memory entry has been assigned and the address and length of data hold in that entry, and see that each command uses the reserved data correctly. Each instruction processor selects commands to be sent to the auxiliary data processor depending upon the conditions of operands. A large amount of data is processed at a high rate, minimizing cache pollution.
摘要翻译：具有内置多入口数据存储器的辅助数据处理器直接连接到主存储器，并且执行从多个指令处理器发送的命令直接访问主存储器。一个数据存储器条目被分配给发出命令的指令处理器，并且响应于命令保留从主存储器获取的数据，使得下一个命令可以使用该数据的一部分。标签电路保存已经分配了数据存储器条目的每个指令处理器的标识符，并且在该条目中保存数据的地址和长度，并且看到每个命令正确地使用保留的数据。每个指令处理器根据操作数的条件选择要发送到辅助数据处理器的命令。以高速率处理大量数据，最大限度地减少高速缓存污染。

9. 发明授权

US4924377A Pipelined instruction processor capable of reading dependent operands in parallel 失效
标题翻译：能够并行读取相关操作数的流水线指令处理器
公开(公告)号：US4924377A
公开(公告)日：1990-05-08
申请号：US687161
申请日：1984-12-28
申请人： Kazunori Kuriyama , Kenichi Wada , Akira Yamaoka
发明人： Kazunori Kuriyama , Kenichi Wada , Akira Yamaoka
IPC分类号： G06F9/34 , G06F9/345 , G06F9/355 , G06F9/38
CPC分类号： G06F9/355 , G06F9/345 , G06F9/383
摘要： Address calculation adders and a buffer storages are each independently provided for each operand of an instruction requiring two or more operands. In the translation instruction processing, the address calculations and operand fetch operations on the first and second operands are substantially asynchronously conducted. Consequently, the overhead that takes place one every n second operand fetch operations can be removed by independently and asynchronously performing the address calculations and operand fetch operations by use of a plurality of address adders. Moreover, the circuit for separating and obtaining a byte from the operand buffer can be dispensed with by adopting an operation procedure in which a byte of the first operand is fetched and is stored in temporary store means that supplies the address adder the data stored therein.
摘要翻译：对于需要两个或多个操作数的指令的每个操作数，地址计算加法器和缓冲存储器都是独立提供的。在转换指令处理中，对第一和第二操作数的地址计算和操作数获取操作基本上异步进行。因此，可以通过使用多个地址加法器独立地和异步地执行地址计算和操作数获取操作来移除每n个第二操作数获取操作发生一次的开销。此外，可以通过采用其中获取第一操作数的字节的操作过程来存储用于从操作数缓冲器分离和获得字节的电路，并将其存储在向地址加法器提供其中存储的数据的临时存储装置中。

10. 发明授权

US5734918A Computer system with an input/output processor which enables direct file transfers between a storage medium and a network 失效
标题翻译：具有输入/输出处理器的计算机系统，其能够在存储介质和网络之间直接传送文件
公开(公告)号：US5734918A
公开(公告)日：1998-03-31
申请号：US504600
申请日：1995-07-20
申请人： Hiroaki Odawara , Moritoshi Yasunaga , Kazunori Kuriyama
发明人： Hiroaki Odawara , Moritoshi Yasunaga , Kazunori Kuriyama
IPC分类号： G06F13/10 , G06F3/06 , G06F13/12 , H04L29/06 , H04L29/08 , G06F15/20
CPC分类号： H04L67/06 , H04L67/1097 , H04L69/16 , H04L69/161 , H04L69/329
摘要： A data processor transfers files at high speeds from a magnetic disk or other storage media to a network and shortens the processing time for the file transfers. An I/O processor includes (i) a channel to which a magnetic disk is connected, (ii) a LAN adapter to which a network is connected, (iii) a switch for switching and connecting the channel and LAN adapter, and (iv) a channel controller for controlling the channel, the LAN adapter, and the switch. The channel controller controls the channel, the LAN adapter, and the switch in accordance with a data transfer start instruction from an instruction processor. The channel reads data from the magnetic disk and transfers it to the LAN adapter via the switch. The LAN adapter sends the data to the network or reads data from the network and transfers it to the channel via the switch. The channel sends the data to the magnetic disk.
摘要翻译：数据处理器以高速将文件从磁盘或其他存储介质传输到网络，并缩短文件传输的处理时间。 I / O处理器包括（i）连接磁盘的通道，（ii）连接网络的LAN适配器，（iii）用于切换和连接通道和LAN适配器的开关，以及（iv ）用于控制信道的通道控制器，LAN适配器和开关。通道控制器根据来自指令处理器的数据传输开始指令控制通道，LAN适配器和开关。通道从磁盘读取数据，并通过交换机将其传输到LAN适配器。 LAN适配器将数据发送到网络或从网络读取数据，并通过交换机将其传输到通道。通道将数据发送到磁盘。

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