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1. 发明授权

US06931722B2 Method of fabricating printed circuit board with mixed metallurgy pads 失效
标题翻译：用混合冶金垫制造印刷电路板的方法
公开(公告)号：US06931722B2
公开(公告)日：2005-08-23
申请号：US10395944
申请日：2003-03-24
申请人： Edward L. Arrington , Anilkumar C. Bhatt , Edmond O. Fey , Kevin T. Knadle , John J. Konrad , Joseph A Kotylo , Jeffrey McKeveny , Jose A. Rios , Amit K. Sarkhel , Andrew M. Seman , Timothy L. Wells
发明人： Edward L. Arrington , Anilkumar C. Bhatt , Edmond O. Fey , Kevin T. Knadle , John J. Konrad , Joseph A Kotylo , Jeffrey McKeveny , Jose A. Rios , Amit K. Sarkhel , Andrew M. Seman , Timothy L. Wells
IPC分类号： H05K3/24 , H05K3/28 , H05K3/34 , H05K3/42 , H05K3/02
CPC分类号： H05K3/243 , H05K3/28 , H05K3/3452 , H05K3/3473 , H05K3/42 , H05K2201/0391 , H05K2203/0315 , H05K2203/0574 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.
摘要翻译：公开了一种制造印刷电路器件的方法，该印刷电路器件包括电绝缘衬底以及形成在衬底顶表面上的第一组，第二组和第三组导体。该方法包括在第二导体组上形成氧化物层; 在氧化物层上形成焊料掩模; 在第一组导体上形成复合层; 以及在所述第三组导体的至少一部分上形成焊料层。

2. 发明授权

US06586683B2 Printed circuit board with mixed metallurgy pads and method of fabrication 有权
公开(公告)号：US06586683B2
公开(公告)日：2003-07-01
申请号：US09844814
申请日：2001-04-27
申请人： Edward L. Arrington , Anilkumar C. Bhatt , Edmond O. Fey , Kevin T. Knadle , John J. Konrad , Joseph A. Kotylo , Jeffrey McKeveny , Jose A. Rios , Amit K. Sarkhel , Andrew M. Seman , Timothy L. Wells
发明人： Edward L. Arrington , Anilkumar C. Bhatt , Edmond O. Fey , Kevin T. Knadle , John J. Konrad , Joseph A. Kotylo , Jeffrey McKeveny , Jose A. Rios , Amit K. Sarkhel , Andrew M. Seman , Timothy L. Wells
IPC分类号： H05K103
CPC分类号： H05K3/243 , H05K3/28 , H05K3/3452 , H05K3/3473 , H05K3/42 , H05K2201/0391 , H05K2203/0315 , H05K2203/0574 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

3. 发明授权

US06492715B1 Integrated semiconductor package 有权
标题翻译：集成半导体封装
公开(公告)号：US06492715B1
公开(公告)日：2002-12-10
申请号：US09660866
申请日：2000-09-13
申请人： Voya R. Markovich , Douglas O. Powell , Amit K. Sarkhel
发明人： Voya R. Markovich , Douglas O. Powell , Amit K. Sarkhel
IPC分类号： H01L2302
CPC分类号： H01L21/563 , H01L23/055 , H01L23/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H01L2924/01078 , H01L2924/15311 , H01L2924/16195 , H01L2924/00 , H01L2224/0401
摘要： The present invention provides an integrated semiconductor module comprising a chip, interposer, and substrate. The module is adapted to be mounted on a traditional circuit card carrying multiple other components. The chip of the present invention can be a conventional IC chip or chip package, including ball grid array packages, and will simply be referred to hereinafter as a “chip.” The interposer of the present invention is a conventional thin film interposer, such as those composed of a polyimide material and fabricated on a glass carrier plate. The substrate of the present invention is a conventional circuitized substrate, such as a BGA or laminate substrate, that is commonly employed in carrying a chip on a circuit card. In its assembled state, the present invention comprises an interposer mounted on top of a substrate with the electrical contacts formed on the lower surface of the interposer positioned in electrical communication with respective ones of electrical contacts formed on the upper surface of the substrate. A non-conductive material, such as an epoxy resin, fills the voids between the interposer and substrate created by the electrical connections. The epoxy resin forms a mechanical bond between the interposer and substrate, thereby enhancing the structural integrity of the unit. Moreover, by filling the voids between the electrical connections, essentially no foreign particles can become entrapped therein and cause electrical malfunctions. Accordingly, the environmental and operational integrity of the unit is also enhanced.
摘要翻译：本发明提供了一种包括芯片，插入器和衬底的集成半导体模块。该模块适于安装在承载多个其他部件的传统电路卡上。本发明的芯片可以是包括球栅阵列封装在内的常规IC芯片或芯片封装，并且在下文中简单地称为“芯片”。本发明的插入件是常规的薄膜插入件，例如由聚酰亚胺材料构成的薄膜插入件，并且制造在玻璃载体板上。本发明的基板是通常用于承载电路卡上的芯片的常规电路化基板，例如BGA或层叠基板。在其组装状态下，本发明包括安装在基板的顶部上的插入件，其中形成在插入件的下表面上的电触点定位成与形成在基板的上表面上的相应电触头电连通。诸如环氧树脂的非导电材料填充由电连接产生的插入件和衬底之间的空隙。环氧树脂在插入物和基材之间形成机械结合，从而提高了单元的结构完整性。此外，通过填充电连接之间的空隙，基本上不会在其中夹带杂质颗粒并引起电气故障。因此，该单位的环境和运营完整性也得到提高。

4. 发明授权

US06784086B2 Lead-free solder structure and method for high fatigue life 有权
标题翻译：无铅焊料结构和高疲劳寿命的方法
公开(公告)号：US06784086B2
公开(公告)日：2004-08-31
申请号：US09779812
申请日：2001-02-08
申请人： Sudipta K. Ray , Amit K. Sarkhel
发明人： Sudipta K. Ray , Amit K. Sarkhel
IPC分类号： H01L2144
CPC分类号： H01L24/10 , B23K35/0244 , B23K35/262 , H01L23/488 , H01L23/49816 , H01L24/13 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/16 , H01L2224/81801 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01067 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H05K3/3436 , H05K3/3463 , H01L2924/00 , H01L2224/05599
摘要： A method and structure for solderably coupling an electronic module (e.g. a ceramic or plastic ball grid array module) to a circuit board. A lead-free solder ball is soldered to the module without using a joining solder to effectuate the soldering. The solder ball comprises a tin-antimony alloy that includes about 3% to about 15% antimony by weight. The solder ball is soldered to the circuit board with a lead-free joiner solder. The joiner solder comprises a tin-silver-copper alloy that includes by weight about 95.5-96.0% tin, about 3.5-4.0% silver, and about 0.5-1.0% copper. The resultant solder connection between the module and the circuit board has a fatigue life of at least about 90% of a fatigue life of a reference structure. The reference structure has a 90Pb/10Sn solder ball joined to both the module and the circuit card by a 63Sn/37Pb joiner solder.
摘要翻译：一种用于将电子模块（例如陶瓷或塑料球栅阵列模块）可焊接地耦合到电路板的方法和结构。将无铅焊球焊接到模块上，而不使用连接焊料来实现焊接。焊球包括包含约3重量％至约15重量％的锑的锡 - 锑合金。焊球用无铅合金焊料焊接到电路板上。合金焊料包括锡 - 银 - 铜合金，其包括重量约95.5-96.0％的锡，约3.5-4.0％的银和约0.5-1.0％的铜。模块和电路板之间的所得焊接连接件的疲劳寿命至少为参考结构的疲劳寿命的约90％。参考结构具有通过63Sn / 37Pb接合焊料连接到模块和电路卡的90Pb / 10Sn焊球。

5. 发明授权

US06433425B1 Electronic package interconnect structure comprising lead-free solders 有权
标题翻译：包括无铅焊料的电子封装互连结构
公开(公告)号：US06433425B1
公开(公告)日：2002-08-13
申请号：US09660558
申请日：2000-09-12
申请人： Amit K. Sarkhel
发明人： Amit K. Sarkhel
IPC分类号： H01L2348
CPC分类号： H05K3/3436 , H01L23/488 , H01L23/49816 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01055 , H01L2924/01322 , H05K3/3463 , H05K2201/10992 , H05K2203/041 , H05K2203/0415 , Y02P70/613 , Y10T428/24917 , H01L2224/05599
摘要： A method and structure for forming an electronic package with an interconnect structure that comprises lead-free solders. The method first forms a module by initially providing a chip carrier, a first joiner solder that is lead-free, and a core interconnect (e.g., solder ball, solder column) that includes a lead-free core solder. The liquidus temperature TIL of the first joiner solder is less than a solidus temperature TCS of the core solder. A first end of the core interconnect is soldered to the chip carrier with the first joiner solder, which includes reflowing the first joiner solder at a reflow temperature that is above TIL and below TCS, followed by cooling the first joiner solder to a temperature that is below a solidus temperature of the first joiner solder. Thus, the module with the soldered core interconnect has been formed. The method then provides a circuit card and a second joiner solder that is lead-free. The liquidus temperature T2L of the second joiner solder is less than TCS. A second end of the core interconnect is soldered to the circuit card with the second joiner solder, which includes reflowing the second joiner solder at a reflow temperature that is above T2L and below TCS, followed by cooling the second joiner solder to a lower temperature that is below a solidus temperature of the second joiner solder.
摘要翻译：一种用于形成具有包括无铅焊料的互连结构的电子封装的方法和结构。该方法首先通过初始提供芯片载体，无铅的第一合金焊料和包括无铅芯焊料的芯互连（例如，焊球，焊料柱）形成模块。第一接合焊料的液相线温度TIL小于芯焊料的固相线温度TCS。核心互连的第一端使用第一接合焊料焊接到芯片载体，其包括以高于TIL并低于TCS的回流温度回流第一接合焊料，然后将第一接合焊料冷却至温度为低于第一接合焊料的固相线温度。因此，已经形成了具有焊接芯互连的模块。该方法然后提供无铅的电路卡和第二接合焊料。第二接合焊料的液相线温度T2L小于TCS。核心互连的第二端用第二接合焊料焊接到电路卡，其包括在高于T2L且低于TCS的回流温度下回流第二接合焊料，然后将第二接合焊料冷却至较低的温度，低于第二接合焊料的固相线温度。

6. 发明授权

US06634543B2 Method of forming metallic z-interconnects for laminate chip packages and boards 有权
公开(公告)号：US06634543B2
公开(公告)日：2003-10-21
申请号：US10040839
申请日：2002-01-07
申请人： Brian E. Curcio , Donald S. Farquhar , Elizabeth F. Foster , Amit K. Sarkhel
发明人： Brian E. Curcio , Donald S. Farquhar , Elizabeth F. Foster , Amit K. Sarkhel
IPC分类号： B23K2000
CPC分类号： H05K3/462 , B23K20/023 , B23K2101/42 , H05K3/244 , H05K3/328 , H05K3/4623 , H05K2201/096
摘要： Deterioration and damage to insulator materials in an interconnection structure having vertical connections due to exposure to heat during bonding of lamina is avoided by performing diffusion bonding of metal pads at plated through holes (PTH) at temperatures below the melting points of conductive material in the bond. Diffusion bonding is achieved during time periods required for processing (e.g. curing or drying) of insulating materials in the laminated structure.

7. 发明授权

US06581821B2 Electronic package interconnect structure comprising lead-free solders 有权
公开(公告)号：US06581821B2
公开(公告)日：2003-06-24
申请号：US10197291
申请日：2002-07-16
申请人： Amit K. Sarkhel
发明人： Amit K. Sarkhel
IPC分类号： B23K3102
CPC分类号： H05K3/3436 , H01L23/488 , H01L23/49816 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01055 , H01L2924/01322 , H05K3/3463 , H05K2201/10992 , H05K2203/041 , H05K2203/0415 , Y02P70/613 , Y10T428/24917 , H01L2224/05599
摘要： A method and structure for forming an electronic package with an interconnect structure that comprises lead-free solders. The method first forms a module by initially providing a chip carrier, a first joiner solder that is lead-free, and a core interconnect (e.g., solder ball, solder column) that includes a lead-free core solder. The liquidus temperature T1L of the first joiner solder is less than a solidus temperature TCS of the core solder. A first end of the core interconnect is soldered to the chip carrier with the first joiner solder, which includes reflowing the first joiner solder at a reflow temperature that is above T1L and below TCS, followed by cooling the first joiner solder to a temperature that is below a solidus temperature of the first joiner solder. Thus, the module with the soldered core interconnect has been formed. The method then provides a circuit card and a second joiner solder that is lead-free. The liquidus temperature T2L of the second joiner solder is less than TCS. A second end of the core interconnect is soldered to the circuit card with the second joiner solder, which includes reflowing the second joiner solder at a reflow temperature that is above T2L and below TCS, followed by cooling the second joiner solder to a lower temperature that is below a solidus temperature of the second joiner solder.

8. 发明授权

US06281581B1 Substrate structure for improving attachment reliability of semiconductor chips and modules 有权
标题翻译：用于提高半导体芯片和模块的附着可靠性的基板结构
公开(公告)号：US06281581B1
公开(公告)日：2001-08-28
申请号：US09388753
申请日：1999-09-02
申请人： Kishor V. Desai , Amit K. Sarkhel
发明人： Kishor V. Desai , Amit K. Sarkhel
IPC分类号： H01L2144
CPC分类号： H01L24/10 , H01L24/13 , H01L24/81 , H01L2224/05655 , H01L2224/13 , H01L2224/13006 , H01L2224/13099 , H01L2224/13111 , H01L2224/81801 , H01L2924/01004 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H05K1/111 , H05K1/112 , H05K3/3436 , H05K2201/09472 , H05K2201/09509 , H05K2201/09736 , H05K2201/09745 , H05K2201/10734 , H05K2201/10992 , H05K2203/041 , Y02P70/611 , Y02P70/613 , H01L2924/00 , H01L2924/00014
摘要： An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.
摘要翻译：用于将半导体芯片或球栅阵列模块粘附到支撑基板上的粘合垫包括阶梯形或锥形结构。该结构由至少一个焊料可湿性金属或其上沉积有焊料的合金层组成。阶梯式或锥形结构防止疲劳裂纹在粘合垫上方的X-Y平面中传播。

9. 发明授权

US06429388B1 High density column grid array connections and method thereof 有权
标题翻译：高密度柱格阵列连接及其方法
公开(公告)号：US06429388B1
公开(公告)日：2002-08-06
申请号：US09564110
申请日：2000-05-03
申请人： Mario J. Interrante , Brenda Peterson , Sudipta K. Ray , William E. Sablinski , Amit K. Sarkhel
发明人： Mario J. Interrante , Brenda Peterson , Sudipta K. Ray , William E. Sablinski , Amit K. Sarkhel
IPC分类号： H01R909
CPC分类号： B23K35/262 , H01L23/488 , H01L23/49811 , H01L2224/05568 , H01L2224/05573 , H01L2224/13109 , H01L2924/00013 , H01L2924/00014 , H01L2924/01322 , H05K3/3426 , H05K3/3436 , H05K3/3463 , H05K3/4015 , H05K2201/10242 , H05K2203/047 , Y02P70/613 , H01L2224/29099 , H01L2224/05599
摘要： The present invention relates generally to a new semiconductor chip carrier connections, where the chip carrier and the second level assembly are made by a surface mount technology. More particularly, the invention encompasses surface mount technologies, such as, Ball Grid Array (BGA), Column Grid Array (CGA), to name a few, where the surface mount technology comprises essentially of a non-solder metallic connection, such as, a copper connection. The present invention is also related to Column Grid Array structures and process thereof.
摘要翻译：本发明一般涉及新的半导体芯片载体连接，其中芯片载体和第二级组件是通过表面贴装技术制成的。更具体地，本发明包括表面贴装技术，例如球栅阵列（BGA），柱栅阵列（CGA），其中表面贴装技术基本上由非焊料金属连接构成，例如，铜连接。本发明还涉及列格阵列结构及其工艺。

10. 发明授权

US06251766B1 Method for improving attachment reliability of semiconductor chips and modules 有权
标题翻译：提高半导体芯片和模块附件可靠性的方法
公开(公告)号：US06251766B1
公开(公告)日：2001-06-26
申请号：US09388755
申请日：1999-09-02
申请人： Kishor V. Desai , Amit K. Sarkhel
发明人： Kishor V. Desai , Amit K. Sarkhel
IPC分类号： H01L2144
CPC分类号： H01L24/10 , H01L24/13 , H01L24/81 , H01L2224/05655 , H01L2224/13 , H01L2224/13006 , H01L2224/13099 , H01L2224/13111 , H01L2224/81801 , H01L2924/01004 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H05K1/111 , H05K1/112 , H05K3/3436 , H05K2201/09472 , H05K2201/09509 , H05K2201/09736 , H05K2201/09745 , H05K2201/10734 , H05K2201/10992 , H05K2203/041 , Y02P70/611 , Y02P70/613 , H01L2924/00 , H01L2924/00014
摘要： An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.
摘要翻译：用于将半导体芯片或球栅阵列模块粘附到支撑基板上的粘合垫包括阶梯形或锥形结构。该结构由至少一个焊料可湿性金属或其上沉积有焊料的合金层组成。台阶或锥形结构防止疲劳裂纹在粘合垫上方的X-Y平面中传播。

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