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1. 发明授权

US06931722B2 Method of fabricating printed circuit board with mixed metallurgy pads 失效
标题翻译：用混合冶金垫制造印刷电路板的方法
公开(公告)号：US06931722B2
公开(公告)日：2005-08-23
申请号：US10395944
申请日：2003-03-24
申请人： Edward L. Arrington , Anilkumar C. Bhatt , Edmond O. Fey , Kevin T. Knadle , John J. Konrad , Joseph A Kotylo , Jeffrey McKeveny , Jose A. Rios , Amit K. Sarkhel , Andrew M. Seman , Timothy L. Wells
发明人： Edward L. Arrington , Anilkumar C. Bhatt , Edmond O. Fey , Kevin T. Knadle , John J. Konrad , Joseph A Kotylo , Jeffrey McKeveny , Jose A. Rios , Amit K. Sarkhel , Andrew M. Seman , Timothy L. Wells
IPC分类号： H05K3/24 , H05K3/28 , H05K3/34 , H05K3/42 , H05K3/02
CPC分类号： H05K3/243 , H05K3/28 , H05K3/3452 , H05K3/3473 , H05K3/42 , H05K2201/0391 , H05K2203/0315 , H05K2203/0574 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.
摘要翻译：公开了一种制造印刷电路器件的方法，该印刷电路器件包括电绝缘衬底以及形成在衬底顶表面上的第一组，第二组和第三组导体。该方法包括在第二导体组上形成氧化物层; 在氧化物层上形成焊料掩模; 在第一组导体上形成复合层; 以及在所述第三组导体的至少一部分上形成焊料层。

2. 发明授权

US06586683B2 Printed circuit board with mixed metallurgy pads and method of fabrication 有权
公开(公告)号：US06586683B2
公开(公告)日：2003-07-01
申请号：US09844814
申请日：2001-04-27
申请人： Edward L. Arrington , Anilkumar C. Bhatt , Edmond O. Fey , Kevin T. Knadle , John J. Konrad , Joseph A. Kotylo , Jeffrey McKeveny , Jose A. Rios , Amit K. Sarkhel , Andrew M. Seman , Timothy L. Wells
发明人： Edward L. Arrington , Anilkumar C. Bhatt , Edmond O. Fey , Kevin T. Knadle , John J. Konrad , Joseph A. Kotylo , Jeffrey McKeveny , Jose A. Rios , Amit K. Sarkhel , Andrew M. Seman , Timothy L. Wells
IPC分类号： H05K103
CPC分类号： H05K3/243 , H05K3/28 , H05K3/3452 , H05K3/3473 , H05K3/42 , H05K2201/0391 , H05K2203/0315 , H05K2203/0574 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

3. 发明授权

US07087441B2 Method of making a circuitized substrate having a plurality of solder connection sites thereon 失效
标题翻译：制造其上具有多个焊接连接部位的电路化基板的方法
公开(公告)号：US07087441B2
公开(公告)日：2006-08-08
申请号：US10968929
申请日：2004-10-21
申请人： John J. Konrad , Joseph A. Kotylo , Jose A. Rios
发明人： John J. Konrad , Joseph A. Kotylo , Jose A. Rios
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L21/486 , H05K3/243 , H05K3/3463 , H05K3/3473 , H05K3/42 , H05K2201/0391 , H05K2203/0542 , H05K2203/0723
摘要： A method of making a circuitized substrate in which two solder deposits, either of the same or different metallurgies, are formed on at least two different metal or metal alloy conductors and PTHs. In an alternative embodiment, the same solder compositions may be deposited on conductor and PTHs of different metal or metal alloy composition. In each embodiment, a single commoning layer (e.g., copper) is used, being partially removed following the first deposition. The solder is deposited using an electroplating process (electroless or electrolytic) and the commoning bar in both depositing steps. An information handling system utilizing the circuitized substrate formed in accordance with the invention is also described.
摘要翻译：一种制造电路化基板的方法，其中在至少两种不同的金属或金属合金导体和PTH上形成两个相同或不同的冶金的焊料沉积物。在替代实施例中，相同的焊料组合物可以沉积在不同金属或金属合金组成的导体和PTH上。在每个实施例中，使用单个共用层（例如铜），在第一次沉积之后被部分去除。在两个沉积步骤中，使用电镀工艺（无电解或电解）和共用条来沉积焊料。还描述了利用根据本发明形成的电路化基板的信息处理系统。

4. 发明申请

US20080241359A1 Method of making circuitized substrate with selected conductors having solder thereon 失效
标题翻译：制造具有在其上具有焊料的所选导体的电路化衬底的方法
公开(公告)号：US20080241359A1
公开(公告)日：2008-10-02
申请号：US11730212
申请日：2007-03-30
申请人： Norman A. Card , Robert J. Harendza , John J. Konrad , Tonya Mosher , Susan Pitely , Jose A. Rios
发明人： Norman A. Card , Robert J. Harendza , John J. Konrad , Tonya Mosher , Susan Pitely , Jose A. Rios
IPC分类号： H01C17/06
CPC分类号： H01C17/065 , H01C1/144 , H01C7/006 , H05K3/243 , H05K3/28 , H05K3/3468 , H05K2201/0391 , H05K2203/044 , H05K2203/0574 , H05K2203/0577
摘要： A method of making a circuitized substrate in which conductors are formed in such a manner that selected ones of the conductors include solder while others do not and are thus adapted for receiving a different form of connection (e.g., wire-bond) than the solder covered conductors. In one embodiment, the solder may be applied in molten form by immersing the substrate within a bath of the solder while in another the solder may be deposited using a screening procedure.
摘要翻译：一种制造电路化衬底的方法，其中导体以这样的方式形成，使得所选择的导体包括焊料，而另一些导体不适于接收不同于覆盖的焊料的不同形式的连接（例如，引线接合）导体在一个实施例中，焊料可以通过将衬底浸入焊料槽中而以熔融形式施加，而在另一种焊料中可以使用筛选程序进行沉积。

5. 发明授权

US07910156B2 Method of making circuitized substrate with selected conductors having solder thereon 失效
标题翻译：制造具有在其上具有焊料的所选导体的电路化衬底的方法
公开(公告)号：US07910156B2
公开(公告)日：2011-03-22
申请号：US11730212
申请日：2007-03-30
申请人： Norman A. Card , Robert J. Harendza , John J. Konrad , Tonya L. Mosher , Susan Pitely , Jose A. Rios
发明人： Norman A. Card , Robert J. Harendza , John J. Konrad , Tonya L. Mosher , Susan Pitely , Jose A. Rios
IPC分类号： B05D5/12
CPC分类号： H01C17/065 , H01C1/144 , H01C7/006 , H05K3/243 , H05K3/28 , H05K3/3468 , H05K2201/0391 , H05K2203/044 , H05K2203/0574 , H05K2203/0577
摘要： A method of making a circuitized substrate in which conductors are formed in such a manner that selected ones of the conductors include solder while others do not and are thus adapted for receiving a different form of connection (e.g., wire-bond) than the solder covered conductors. In one embodiment, the solder may be applied in molten form by immersing the substrate within a bath of the solder while in another the solder may be deposited using a screening procedure.
摘要翻译：一种制造电路化衬底的方法，其中导体以这样的方式形成，使得所选择的导体包括焊料，而另一些导体不适于接收不同于覆盖的焊料的不同形式的连接（例如，引线接合）导体在一个实施例中，焊料可以通过将衬底浸入焊料槽中而以熔融形式施加，而在另一种焊料中可以使用筛选程序进行沉积。

6. 发明授权

US06421622B1 Dynamic attitude measurement sensor and method 失效
标题翻译：动态姿态测量传感器及方法
公开(公告)号：US06421622B1
公开(公告)日：2002-07-16
申请号：US09326738
申请日：1999-06-04
申请人： Michael A. Horton , Jose A. Rios , Jin Song
发明人： Michael A. Horton , Jose A. Rios , Jin Song
IPC分类号： G01P2100
CPC分类号： G01C21/16
摘要： A method and system senses the attitude of an accelerating object. Attitude sensing is accomplished by measuring acceleration in three orthogonal axes and measuring angular rate about each such axis to compute attitude accurately relative to a vertical axis. The system includes accelerometers and angular rate sensors for sensing the acceleration and the angular rate, respectively, of the object. A processor updates a quarternion representation of attitude based upon the angular rate of the object and a corrective rate signal to obtain the attitude of the object. Temperature compensation and frequency compensation may also be performed to update the quarternion.
摘要翻译：一种方法和系统感测加速对象的姿态。姿态感测通过测量三个正交轴中的加速度并测量围绕每个这样的轴的角速度来实现，以相对于垂直轴准确地计算姿态。该系统包括分别用于感测物体的加速度和角速度的加速度计和角速度传感器。处理器基于对象的角速率和校正速率信号更新态度的季节表示以获得对象的姿态。也可以进行温度补偿和频率补偿来更新季度。

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