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1. 发明申请

US20090089514A1 Implementing Asynchronous Request for Forcing Dynamic Memory into Self Refresh 审中-公开
标题翻译：实现异步请求强制动态内存进入自刷新
公开(公告)号：US20090089514A1
公开(公告)日：2009-04-02
申请号：US11864738
申请日：2007-09-28
申请人： Durgesh Srivastava , Niall McDonnell , Will Akin , Mark Schmisseur
发明人： Durgesh Srivastava , Niall McDonnell , Will Akin , Mark Schmisseur
IPC分类号： G06F12/00
CPC分类号： G06F13/4234 , G06F1/30 , Y02D10/14 , Y02D10/151
摘要： In some embodiments a memory controller receives a signal indicating a power condition of a system. In response to the received signal the memory controller controls a clock enable signal to a memory, allows only already issued memory controller signals to finish, and forces the memory into a self refresh. A transition is made such that power is only provided to the memory controller and to the memory, and no power is provided to any other components in the system. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，存储器控制器接收指示系统的功率状况的信号。响应于接收到的信号，存储器控制器控制到存储器的时钟使能信号，仅允许已经发出的存储器控制器信号完成，并强制存储器进行自刷新。进行转换，使得仅向存储器控制器和存储器提供电力，并且不向系统中的任何其他组件提供电力。描述和要求保护其他实施例。

2. 发明申请

US20050053083A1 Systems and methods for using HDLC channel context to simultaneously process multiple HDLC channels 有权
标题翻译：使用HDLC信道上下文同时处理多个HDLC信道的系统和方法
公开(公告)号：US20050053083A1
公开(公告)日：2005-03-10
申请号：US10655565
申请日：2003-09-04
申请人： Ronan O'Ceallaigh , Daniel Borkowski , Niall McDonnell
发明人： Ronan O'Ceallaigh , Daniel Borkowski , Niall McDonnell
IPC分类号： H04L12/28 , H04L29/06 , H04L29/08
CPC分类号： H04L69/12 , H04L69/324
摘要： Systems and methods are disclosed for using High-level Data Link Control (HDLC) channel context information to simultaneously process multiple HDLC channels. Preferred embodiments of the present invention enable a single network processing engine to process multiple HDLC channels. The current state of the HDLC channel can be evaluated, stored, and restored, which means that the processing of a channel can be halted, the channel state read and stored, and the state of a different channel written to the processing engine. This allows the engine to begin processing a new channel, and then, at a later stage, restore the state of the original channel and resume processing.
摘要翻译：公开了使用高级数据链路控制（HDLC）信道上下文信息来同时处理多个HDLC信道的系统和方法。本发明的优选实施例使单个网络处理引擎能够处理多个HDLC信道。可以评估，存储和恢复HDLC信道的当前状态，这意味着可以停止对信道的处理，读取和存储信道状态以及写入处理引擎的不同信道的状态。这允许引擎开始处理新的通道，然后在稍后的阶段恢复原始通道的状态并恢复处理。

3. 发明申请

US20060090094A1 Real-time fail-over recovery for a media area network 有权
标题翻译：媒体区域网络的实时故障切换恢复
公开(公告)号：US20060090094A1
公开(公告)日：2006-04-27
申请号：US10522973
申请日：2003-07-03
申请人： Niall McDonnell , David Crowther , Daniel Bame , Robert Wood
发明人： Niall McDonnell , David Crowther , Daniel Bame , Robert Wood
IPC分类号： G06F11/00
CPC分类号： G06F11/201 , G06F11/2007 , G06F11/2053
摘要： A media area network includes a storage system having at least one storage device for storing digitized information. A host bus adapter provides a link between the storage system and a host system that provides overall control of the media area network. Within the host bus adapter, a lower-level port driver monitors communications between the storage system and the host bus adapter. In the event of a communications failure, the lower-level port driver initiates switching from a failed port to an alternative port, thereby achieving fail-over recovery. Allocating the responsibility for fail-over recovery to the lower-level port driver assures timely handling of port failures, thereby reducing potential latency delays.
摘要翻译：媒体区域网络包括具有用于存储数字化信息的至少一个存储设备的存储系统。主机总线适配器提供存储系统和提供媒体区域网络的整体控制的主机系统之间的链接。在主机总线适配器中，较低级别的端口驱动程序监视存储系统和主机总线适配器之间的通信。在通信故障的情况下，下级端口驱动程序启动从故障端口切换到备用端口，从而实现故障切换恢复。将故障切换恢复责任分配给下级端口驱动程序，确保及时处理端口故障，从而减少潜在的延迟延迟。

4. 发明申请

US20050203960A1 Systems and methods that synchronize data with representations of the data 有权
标题翻译：将数据与数据表示同步的系统和方法
公开(公告)号：US20050203960A1
公开(公告)日：2005-09-15
申请号：US10796537
申请日：2004-03-09
申请人： Carlos Suarez , Niall McDonnell , Jack Greenfield , Ian Bavey , Jing Fan
发明人： Carlos Suarez , Niall McDonnell , Jack Greenfield , Ian Bavey , Jing Fan
IPC分类号： G06F17/30
CPC分类号： G06F8/33 , Y10S707/99931 , Y10S707/99954
摘要： The present invention provides systems and methods that synchronize modifications between electronic data and one or more associated data representations. Synchronization comprises translating modification made to the data or a representation to the representations or the data and other representations. A mapping engine is employed to facilitate modification translation, wherein the mapping engine utilizes data-representation relationships, which declaratively described the relationship between data and respective representations. Such relationships can be stored in markup language (e.g., xml) or as a memory string, for example. Modifications can be translated via a continuous technique, wherein translation occurs upon transaction commitment or via an explicit technique, wherein translation occurs upon an explicit request. The systems and methods further employ an adapter that facilitates communication between the mapping engine and the representation and a handler store that provides various handlers that facilitates communication between the mapping engine and data.
摘要翻译：本发明提供了同步电子数据与一个或多个相关数据表示之间的修改的系统和方法。同步包括将对数据的修改或对表示或数据和其他表示的表示进行翻译。使用映射引擎来促进修改翻译，其中映射引擎利用数据表示关系，其声明地描述数据和各个表示之间的关系。这样的关系可以例如以标记语言（例如，xml）或存储器字符串存储。修改可以通过连续技术进行翻译，其中翻译发生在交易承诺或经由显式技术时，其中翻译发生在显式请求时。系统和方法还采用促进映射引擎和表示之间的通信的适配器以及提供有助于映射引擎和数据之间的通信的各种处理程序的处理程序存储器。

5. 发明公开

US20240134648A1 IMPLEMENTING HETEROGENEOUS INSTRUCTION SETS IN HETEROGENEOUS COMPUTE ARCHITECTURES 审中-公开
公开(公告)号：US20240134648A1
公开(公告)日：2024-04-25
申请号：US18398107
申请日：2023-12-27
申请人： Adrian C. Hoban , Thijs Metsch , Francesc Guim Bernat , Niall McDonnell , Gershon Schatzberg
发明人： Adrian C. Hoban , Thijs Metsch , Francesc Guim Bernat , Niall McDonnell , Gershon Schatzberg
IPC分类号： G06F9/30 , G06F15/80
CPC分类号： G06F9/3017 , G06F15/8038
摘要： In one embodiment, an apparatus includes a plurality of processing cores, where each processing core is capable of executing at least one of a subset of an instruction set architecture (ISA). The apparatus also includes hardware circuitry to determine, during runtime, whether a thread comprising instructions of a particular ISA subset can execute on a particular processing core, and based on the determination, indicate a capability of the thread to be executed on the particular processing core in subsequent executions.

6. 发明申请

US20070143335A1 Partition-based undo of partitioned object graph 有权
标题翻译：分区对象图的基于分区的撤销
公开(公告)号：US20070143335A1
公开(公告)日：2007-06-21
申请号：US11305454
申请日：2005-12-16
申请人： Steve Antoch , Jack Greenfield , Keith Hamilton , George Mathew , Niall McDonnell , Ramesh Rajagopal
发明人： Steve Antoch , Jack Greenfield , Keith Hamilton , George Mathew , Niall McDonnell , Ramesh Rajagopal
IPC分类号： G06F7/00
CPC分类号： G06F9/451
摘要： The performing of actions on an object graph that contains multiple objects. The objects are categorized into partitions. Taking into account the partitions, a particular non-final action performed on the object graph may be undone without necessarily first undoing all of the one or more subsequent actions. Instead, if the subsequent actions involved objects of different partitions than the objects that were affected by the particular action desired to be undone, the particular action may be undone without undoing the subsequent actions.
摘要翻译：在包含多个对象的对象图上执行操作。对象被分成分区。考虑到分区，可以撤销在对象图上执行的特定非最终动作，而不必首先撤消所有一个或多个后续动作。相反，如果后续操作涉及不同分区的对象，而不是受特定操作影响的对象需要撤消，则特定操作可以撤消，而不会撤消后续操作。

7. 发明申请

US20050278503A1 Coprocessor bus architecture 审中-公开
标题翻译：协处理器总线架构
公开(公告)号：US20050278503A1
公开(公告)日：2005-12-15
申请号：US10403428
申请日：2003-03-31
申请人： Niall McDonnell
发明人： Niall McDonnell
IPC分类号： G06F9/38 , G06F15/00
CPC分类号： G06F9/3881
摘要： According to some embodiments, a coprocessor bus architecture is provided.
摘要翻译：根据一些实施例，提供协处理器总线架构。

8. 发明申请

US20170286337A1 TECHNOLOGIES FOR A DISTRIBUTED HARDWARE QUEUE MANAGER 审中-公开
公开(公告)号：US20170286337A1
公开(公告)日：2017-10-05
申请号：US15087154
申请日：2016-03-31
申请人： Ren Wang , Yipeng Wang , Jr-Shian Tsai , Andrew Herdrich , Tsung-Yuan Tai , Niall McDonnell , Stephen Van Doren , David Sonnier , Debra Bernstein , Hugh Wilkinson , Narender Vangati , Stephen Miller , Gage Eads , Andrew Cunningham , Jonathan Kenny , Bruce Richardson , William Burroughs , Joseph Hasting , An Yan , James Clee , Te Ma , Jerry Pirog , Jamison Whitesell
发明人： Ren Wang , Yipeng Wang , Jr-Shian Tsai , Andrew Herdrich , Tsung-Yuan Tai , Niall McDonnell , Stephen Van Doren , David Sonnier , Debra Bernstein , Hugh Wilkinson , Narender Vangati , Stephen Miller , Gage Eads , Andrew Cunningham , Jonathan Kenny , Bruce Richardson , William Burroughs , Joseph Hasting , An Yan , James Clee , Te Ma , Jerry Pirog , Jamison Whitesell
IPC分类号： G06F13/36 , G06F13/40 , G06F12/10 , G06F13/24
CPC分类号： G06F13/36 , G06F12/1027 , G06F13/24 , G06F13/4004 , G06F2212/1021 , G06F2212/50 , G06F2212/68
摘要： Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

9. 发明授权

US07162502B2 Systems and methods that synchronize data with representations of the data 有权
标题翻译：将数据与数据表示同步的系统和方法
公开(公告)号：US07162502B2
公开(公告)日：2007-01-09
申请号：US10796537
申请日：2004-03-09
申请人： Carlos Garcia Jurado Suarez , Niall McDonnell , Jack Joseph J. Greenfield , Ian M. Bavey , Jing Fan
发明人： Carlos Garcia Jurado Suarez , Niall McDonnell , Jack Joseph J. Greenfield , Ian M. Bavey , Jing Fan
IPC分类号： G06F17/00 , G06F17/30
CPC分类号： G06F8/33 , Y10S707/99931 , Y10S707/99954
摘要： The present invention provides systems and methods that synchronize modifications between electronic data and one or more associated data representations. Synchronization comprises translating modification made to the data or a representation to the representations or the data and other representations. A mapping engine is employed to facilitate modification translation, wherein the mapping engine utilizes data-representation relationships, which declaratively described the relationship between data and respective representations. Such relationships can be stored in markup language (e.g., xml) or as a memory string, for example. Modifications can be translated via a continuous technique, wherein translation occurs upon transaction commitment or via an explicit technique, wherein translation occurs upon an explicit request. The systems and methods further employ an adapter that facilitates communication between the mapping engine and the representation and a handler store that provides various handlers that facilitates communication between the mapping engine and data.
摘要翻译：本发明提供了同步电子数据与一个或多个相关数据表示之间的修改的系统和方法。同步包括将对数据的修改或对表示或数据和其他表示的表示进行翻译。使用映射引擎来促进修改翻译，其中映射引擎利用数据表示关系，其声明地描述数据和各个表示之间的关系。这样的关系可以例如以标记语言（例如，xml）或存储器字符串存储。修改可以通过连续技术进行翻译，其中翻译发生在交易承诺或经由显式技术时，其中翻译发生在显式请求时。系统和方法还采用促进映射引擎和表示之间的通信的适配器以及提供有助于映射引擎和数据之间的通信的各种处理程序的处理程序存储器。

10. 发明申请

US20050105546A1 Timeslot assignment 失效
标题翻译：时间段分配
公开(公告)号：US20050105546A1
公开(公告)日：2005-05-19
申请号：US10716376
申请日：2003-11-18
申请人： Niall McDonnell
发明人： Niall McDonnell
IPC分类号： H04L12/43 , H04L12/56 , H04Q11/04
CPC分类号： H04L47/6215 , H04L12/43 , H04L47/2416 , H04L47/2425 , H04L47/2441 , H04L47/32 , H04L49/90 , H04L49/901 , H04Q11/04 , H04Q2213/13174 , H04Q2213/13292 , H04Q2213/13392 , H04Q2213/13393
摘要： An apparatus and method includes receiving frames from multiple channels, each frame partitioned into multiple timeslots, reading a timeslot lookup table including an entry that specifies an assignment associated with each timeslot, and storing the data associated with a particular timeslot in a memory location based on the assignment.
摘要翻译：一种装置和方法包括从多个信道接收帧，将每个帧划分成多个时隙，读取包括指定与每个时隙相关联的分配的条目的时隙查找表，以及基于特定时隙与特定时隙相关联的数据存储在存储器位置中分配。

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