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1. 发明申请

US20170286337A1 TECHNOLOGIES FOR A DISTRIBUTED HARDWARE QUEUE MANAGER 审中-公开
公开(公告)号：US20170286337A1
公开(公告)日：2017-10-05
申请号：US15087154
申请日：2016-03-31
申请人： Ren Wang , Yipeng Wang , Jr-Shian Tsai , Andrew Herdrich , Tsung-Yuan Tai , Niall McDonnell , Stephen Van Doren , David Sonnier , Debra Bernstein , Hugh Wilkinson , Narender Vangati , Stephen Miller , Gage Eads , Andrew Cunningham , Jonathan Kenny , Bruce Richardson , William Burroughs , Joseph Hasting , An Yan , James Clee , Te Ma , Jerry Pirog , Jamison Whitesell
发明人： Ren Wang , Yipeng Wang , Jr-Shian Tsai , Andrew Herdrich , Tsung-Yuan Tai , Niall McDonnell , Stephen Van Doren , David Sonnier , Debra Bernstein , Hugh Wilkinson , Narender Vangati , Stephen Miller , Gage Eads , Andrew Cunningham , Jonathan Kenny , Bruce Richardson , William Burroughs , Joseph Hasting , An Yan , James Clee , Te Ma , Jerry Pirog , Jamison Whitesell
IPC分类号： G06F13/36 , G06F13/40 , G06F12/10 , G06F13/24
CPC分类号： G06F13/36 , G06F12/1027 , G06F13/24 , G06F13/4004 , G06F2212/1021 , G06F2212/50 , G06F2212/68
摘要： Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

2. 发明申请

US20170192921A1 MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE 审中-公开
公开(公告)号：US20170192921A1
公开(公告)日：2017-07-06
申请号：US14987676
申请日：2016-01-04
申请人： Ren Wang , Yipeng Wang , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
发明人： Ren Wang , Yipeng Wang , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
IPC分类号： G06F13/37 , G06F13/16 , G06F12/08
CPC分类号： G06F13/37 , G06F9/3004 , G06F9/46 , G06F12/04 , G06F12/0811 , G06F12/0868 , G06F13/1642 , G06F13/1673 , G06F2212/283 , G06F2212/6046
摘要： Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

3. 发明申请

US20070276850A1 Methods and apparatus for updating data structures during in-service upgrade of software in network processor 有权
标题翻译：网络处理器软件在线升级过程中更新数据结构的方法与装置
公开(公告)号：US20070276850A1
公开(公告)日：2007-11-29
申请号：US11412762
申请日：2006-04-27
申请人： Rajarshi Bhattacharya , David Sonnier , Narender Vangati
发明人： Rajarshi Bhattacharya , David Sonnier , Narender Vangati
IPC分类号： G06F7/00
CPC分类号： G06F8/656
摘要： Improved techniques are disclosed for performing an in-service upgrade of software associated with a network or packet processor. By way of example, a method of managing data structures associated with code executable on a packet processor includes the following steps. Data structures in the code are identified as being one of static data structures and non-static data structures, wherein a static data structure includes a data structure that is not changed during execution of the packet processor code and a non-static data structure includes a data structure that is changed during execution of the packet processor code. One or more data structures associated with the packet processor code are managed in a manner specific to the identification of the one or more data structures as static data structures or non-static data structures. At least a portion of the data structures may include tree structures.
摘要翻译：公开了用于执行与网络或分组处理器相关联的软件的在职升级的改进的技术。作为示例，管理与分组处理器上可执行的代码相关联的数据结构的方法包括以下步骤。代码中的数据结构被识别为静态数据结构和非静态数据结构之一，其中静态数据结构包括在分组处理器代码的执行期间不改变的数据结构，并且非静态数据结构包括数据结构在分组处理器代码执行期间发生变化。与分组处理器代码相关联的一个或多个数据结构以特定于一个或多个数据结构的标识作为静态数据结构或非静态数据结构的方式进行管理。数据结构的至少一部分可以包括树结构。

4. 发明申请

US20070255764A1 Methods and apparatus for performing in-service upgrade of software in network processor 有权
标题翻译：在网络处理器中执行软件在线升级的方法和装置
公开(公告)号：US20070255764A1
公开(公告)日：2007-11-01
申请号：US11412915
申请日：2006-04-27
申请人： David Sonnier , Narender Vangati
发明人： David Sonnier , Narender Vangati
IPC分类号： G06F17/30
CPC分类号： G06F8/656
摘要： Improved techniques are disclosed for performing an in-service upgrade of software associated with a network or packet processor. By way of example, a method of performing an in-service upgrade of code, storable in a memory associated with a packet processor and executable on the packet processor, from a first code version to a second code version, includes the following steps. A first step includes preparing for the upgrade by generating one or more write operations to effectuate the code upgrade from the first code version to the second code version. A second step includes updating the code from the first code version to the second code version by propagating the one or more write operations to the packet processor. A third step includes cleaning up after the updating step by reclaiming one or more memory locations available after the update step. As such, the storage of only a single version of the code in the memory associated with the packet processor is required.
摘要翻译：公开了用于执行与网络或分组处理器相关联的软件的在职升级的改进的技术。作为示例，执行可存储在与分组处理器相关联并且可在分组处理器上执行的存储器中的代码的从第一代码版本到第二代码版本的代码的在役升级的方法包括以下步骤。第一步包括通过生成一个或多个写入操作来准备升级，以实现从第一代码版本到第二代码版本的代码升级。第二步包括通过将一个或多个写入操作传播到分组处理器来将代码从第一代码版本更新为第二代码版本。第三步包括在更新步骤之后通过回收在更新步骤之后可用的一个或多个存储器位置进行清理。因此，仅需要在与分组处理器相关联的存储器中存储单个版本的代码。

5. 发明授权

US08868889B2 Instruction breakpoints in a multi-core, multi-thread network communications processor architecture 有权
标题翻译：指令断点在多核，多线程网络通信处理器架构中
公开(公告)号：US08868889B2
公开(公告)日：2014-10-21
申请号：US12976045
申请日：2010-12-22
申请人： Deepak Mital , Te Khac Ma , Narender Vangati , William Burroughs
发明人： Deepak Mital , Te Khac Ma , Narender Vangati , William Burroughs
IPC分类号： G06F9/38 , G06F15/167 , H04L12/873
CPC分类号： G06F15/167 , G06F9/3851 , G06F9/3885 , H04L47/522
摘要： Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate threads of contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes instructions corresponding to threads received from the scheduler. The multi-thread instruction engine executes instructions by fetching an instruction of the thread from an instruction memory of the packet classifier and determining whether a breakpoint mode of the network processor is enabled. If the breakpoint mode is enabled, and breakpoint indicator of the fetched instruction is set, the packet classifier enters a breakpoint mode. Otherwise, if the breakpoint indicator of the fetched instruction is not set, the multi-thread instruction engine executes the fetched instruction.
摘要翻译：描述的实施例提供了一种用于生成与每个接收的分组相对应的任务的网络处理器的分组分类器。分组分类器包括调度器，用于从网络处理器的多个处理模块生成对应于由分组分类器接收到的任务的上下文的线程。多线程指令引擎处理与从调度程序接收到的线程相对应的指令。多线程指令引擎通过从分组分类器的指令存储器取出线程的指令来执行指令，并且确定是否使能网络处理器的断点模式。如果断点模式被使能，并且获取的指令的断点指示器被设置，则分组分类器进入断点模式。否则，如果未设置获取的指令的断点指示符，则多线程指令引擎执行读取的指令。

6. 发明授权

US08505013B2 Reducing data read latency in a network communications processor architecture 有权
标题翻译：降低网络通信处理器架构中的数据读延迟
公开(公告)号：US08505013B2
公开(公告)日：2013-08-06
申请号：US12975823
申请日：2010-12-22
申请人： Steven Pollock , William Burroughs , Deepak Mital , Te Khac Ma , Narender Vangati , Larry King
发明人： Steven Pollock , William Burroughs , Deepak Mital , Te Khac Ma , Narender Vangati , Larry King
IPC分类号： G06F9/46 , G06F12/06
CPC分类号： G06F15/167 , G06F9/32 , G06F9/3851 , G06F9/3885 , G06F9/46 , G06F12/10 , H04L12/56 , H04L47/2441
摘要： Described embodiments provide address translation for data stored in at least one shared memory of a network processor. A processing module of the network processor generates tasks corresponding to each of a plurality of received packets. A packet classifier generates contexts for each task, each context associated with a thread of instructions to apply to the corresponding packet. A first subset of instructions is stored in a tree memory within the at least one shared memory. A second subset of instructions is stored in a cache within a multi-thread engine of the packet classifier. The multi-thread engine maintains status indicators corresponding to the first and second subsets of instructions within the cache and the tree memory and, based on the status indicators, accesses a lookup table while processing a thread to translate between an instruction number and a physical address of the instruction in the first and second subset of instructions.
摘要翻译：描述的实施例为存储在网络处理器的至少一个共享存储器中的数据提供地址转换。网络处理器的处理模块生成与多个接收到的分组中的每一个对应的任务。分组分类器为每个任务生成上下文，每个上下文与指令线程相关联以应用于相应的分组。指令的第一子集被存储在所述至少一个共享存储器内的树存储器中。指令的第二子集存储在分组分类器的多线程引擎内的高速缓存中。多线程引擎保持与高速缓存和树存储器中的第一和第二指令子集相对应的状态指示符，并且基于状态指示符，在处理线程以在指令数和物理地址之间转换时，访问查找表在指令的第一和第二子集中的指令。

7. 发明申请

US20110225394A1 INSTRUCTION BREAKPOINTS IN A MULTI-CORE, MULTI-THREAD NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE 有权
标题翻译：多核心，多线程网络通信处理器架构中的指导性突破
公开(公告)号：US20110225394A1
公开(公告)日：2011-09-15
申请号：US12976045
申请日：2010-12-22
申请人： Deepak Mital , Te Khac Ma , Narender Vangati , William Burroughs
发明人： Deepak Mital , Te Khac Ma , Narender Vangati , William Burroughs
IPC分类号： G06F9/312
CPC分类号： G06F15/167 , G06F9/3851 , G06F9/3885 , H04L47/522
摘要： Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate threads of contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes instructions corresponding to threads received from the scheduler. The multi-thread instruction engine executes instructions by fetching an instruction of the thread from an instruction memory of the packet classifier and determining whether a breakpoint mode of the network processor is enabled. If the breakpoint mode is enabled, and breakpoint indicator of the fetched instruction is set, the packet classifier enters a breakpoint mode. Otherwise, if the breakpoint indicator of the fetched instruction is not set, the multi-thread instruction engine executes the fetched instruction.
摘要翻译：描述的实施例提供了一种用于生成与每个接收的分组相对应的任务的网络处理器的分组分类器。分组分类器包括调度器，用于从网络处理器的多个处理模块生成对应于由分组分类器接收到的任务的上下文的线程。多线程指令引擎处理与从调度程序接收到的线程相对应的指令。多线程指令引擎通过从分组分类器的指令存储器取出线程的指令来执行指令，并且确定是否使能网络处理器的断点模式。如果断点模式被使能，并且获取的指令的断点指示符被设置，则分组分类器进入断点模式。否则，如果未设置获取的指令的断点指示符，则多线程指令引擎执行读取的指令。

8. 发明申请

US20110225588A1 REDUCING DATA READ LATENCY IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE 有权
标题翻译：在网络通信处理器架构中减少数据读取延迟
公开(公告)号：US20110225588A1
公开(公告)日：2011-09-15
申请号：US12975823
申请日：2010-12-22
申请人： Steven Pollock , William Burroughs , Deepak Mital , Te Khac Ma , Narender Vangati , Larry King
发明人： Steven Pollock , William Burroughs , Deepak Mital , Te Khac Ma , Narender Vangati , Larry King
IPC分类号： G06F9/46
CPC分类号： G06F15/167 , G06F9/32 , G06F9/3851 , G06F9/3885 , G06F9/46 , G06F12/10 , H04L12/56 , H04L47/2441
摘要： Described embodiments provide address translation for data stored in at least one shared memory of a network processor. A processing module of the network processor generates tasks corresponding to each of a plurality of received packets. A packet classifier generates contexts for each task, each context associated with a thread of instructions to apply to the corresponding packet. A first subset of instructions is stored in a tree memory within the at least one shared memory. A second subset of instructions is stored in a cache within a multi-thread engine of the packet classifier. The multi-thread engine maintains status indicators corresponding to the first and second subsets of instructions within the cache and the tree memory and, based on the status indicators, accesses a lookup table while processing a thread to translate between an instruction number and a physical address of the instruction in the first and second subset of instructions.
摘要翻译：描述的实施例为存储在网络处理器的至少一个共享存储器中的数据提供地址转换。网络处理器的处理模块生成与多个接收到的分组中的每一个对应的任务。分组分类器为每个任务生成上下文，每个上下文与指令线程相关联以应用于相应的分组。指令的第一子集被存储在所述至少一个共享存储器内的树存储器中。指令的第二子集存储在分组分类器的多线程引擎内的高速缓存中。多线程引擎保持与高速缓存和树存储器中的第一和第二指令子集相对应的状态指示符，并且基于状态指示符，在处理线程以在指令数和物理地址之间转换时，访问查找表在指令的第一和第二子集中的指令。

9. 发明申请

US20050114655A1 Directed graph approach for constructing a tree representation of an access control list 失效
标题翻译：用于构建访问控制列表的树表示的定向图方法
公开(公告)号：US20050114655A1
公开(公告)日：2005-05-26
申请号：US10723160
申请日：2003-11-26
申请人： Stephen Miller , Narender Vangati
发明人： Stephen Miller , Narender Vangati
IPC分类号： H04K1/00 , H04L9/00 , H04L29/06
CPC分类号： H04L63/0263 , G06F2221/2141
摘要： Techniques are disclosed for generating a representation of an access control list, the representation being utilizable in a network processor or other type of processor to perform packet filtering or other type of access control list based function. A plurality of rules of the access control list are determined, each of at least a subset of the rules having a plurality of fields and a corresponding action. The rules are processed to generate a multi-level tree representation of the access control list, in which each of one or more of the levels of the tree representation is associated with a corresponding one of the fields. At least one level of the tree representation comprises a plurality of nodes, with two or more of the nodes of that level having a common subtree, and the tree representation including only a single copy of that subtree. The tree representation is characterizable as a directed graph in which each of the two nodes having the common subtree points to the single copy of the common subtree.
摘要翻译：公开了用于生成访问控制列表的表示的技术，所述表示可在网络处理器或其他类型的处理器中使用以执行分组过滤或基于其他类型的基于访问控制列表的功能。确定访问控制列表的多个规则，规则的至少一个子集中的每一个具有多个字段和相应的动作。处理规则以生成访问控制列表的多级树表示，其中树表示的一个或多个级别中的每一个与相应的一个字段相关联。树表示的至少一个级别包括多个节点，该级别的两个或多个节点具有公共子树，并且树表示仅包含该子树的单个副本。树表示是可定性的，其中具有共同子树的两个节点中的每一个都指向公共子树的单个副本。

10. 发明申请

US20050114657A1 Access control list constructed as a tree of matching tables 有权
标题翻译：访问控制列表构造为匹配表的树
公开(公告)号：US20050114657A1
公开(公告)日：2005-05-26
申请号：US10723150
申请日：2003-11-26
申请人： Vinoj Kumar , Narender Vangati
发明人： Vinoj Kumar , Narender Vangati
IPC分类号： H04L9/00 , H04L29/06
CPC分类号： H04L63/0227 , H04L63/0245
摘要： Techniques are disclosed for generating a representation of an access control list, the representation being utilizable in a network processor or other type of processor to perform packet filtering or other type of access control list based function. A plurality of rules of the access-control list are determined, each of at least a subset of the rules having a plurality of fields and a corresponding action, and the rules are processed to generate a multi-level tree representation of the access control list, in which each of one or more of the levels of the tree representation is associated with a corresponding one of the fields. At least one level of the tree representation other than a root level of the tree representation comprises a plurality of nodes, with at least two of the nodes at that level each having a separate matching table associated therewith.
摘要翻译：公开了用于生成访问控制列表的表示的技术，所述表示可在网络处理器或其他类型的处理器中使用以执行分组过滤或基于其他类型的基于访问控制列表的功能。确定访问控制列表的多个规则，规则的至少一个子集中的每一个具有多个字段和对应的动作，并且处理规则以生成访问控制列表的多级树表示，其中树表示的一个或多个级别中的每一个与相应的一个字段相关联。除了树表示的根级别之外的树形表示的至少一个级别包括多个节点，其中该级别的至少两个节点具有与之相关联的单独的匹配表。

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