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1. 发明申请

US20170286337A1 TECHNOLOGIES FOR A DISTRIBUTED HARDWARE QUEUE MANAGER 审中-公开
公开(公告)号：US20170286337A1
公开(公告)日：2017-10-05
申请号：US15087154
申请日：2016-03-31
申请人： Ren Wang , Yipeng Wang , Jr-Shian Tsai , Andrew Herdrich , Tsung-Yuan Tai , Niall McDonnell , Stephen Van Doren , David Sonnier , Debra Bernstein , Hugh Wilkinson , Narender Vangati , Stephen Miller , Gage Eads , Andrew Cunningham , Jonathan Kenny , Bruce Richardson , William Burroughs , Joseph Hasting , An Yan , James Clee , Te Ma , Jerry Pirog , Jamison Whitesell
发明人： Ren Wang , Yipeng Wang , Jr-Shian Tsai , Andrew Herdrich , Tsung-Yuan Tai , Niall McDonnell , Stephen Van Doren , David Sonnier , Debra Bernstein , Hugh Wilkinson , Narender Vangati , Stephen Miller , Gage Eads , Andrew Cunningham , Jonathan Kenny , Bruce Richardson , William Burroughs , Joseph Hasting , An Yan , James Clee , Te Ma , Jerry Pirog , Jamison Whitesell
IPC分类号： G06F13/36 , G06F13/40 , G06F12/10 , G06F13/24
CPC分类号： G06F13/36 , G06F12/1027 , G06F13/24 , G06F13/4004 , G06F2212/1021 , G06F2212/50 , G06F2212/68
摘要： Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

2. 发明申请

US20170192921A1 MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE 审中-公开
公开(公告)号：US20170192921A1
公开(公告)日：2017-07-06
申请号：US14987676
申请日：2016-01-04
申请人： Ren Wang , Yipeng Wang , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
发明人： Ren Wang , Yipeng Wang , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
IPC分类号： G06F13/37 , G06F13/16 , G06F12/08
CPC分类号： G06F13/37 , G06F9/3004 , G06F9/46 , G06F12/04 , G06F12/0811 , G06F12/0868 , G06F13/1642 , G06F13/1673 , G06F2212/283 , G06F2212/6046
摘要： Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

3. 发明授权

US08677075B2 Memory manager for a network communications processor architecture 有权
标题翻译：用于网络通信处理器架构的内存管理器
公开(公告)号：US08677075B2
公开(公告)日：2014-03-18
申请号：US13359690
申请日：2012-01-27
申请人： Deepak Mital , William Burroughs , David Sonnier , Steven Pollock , David Brown , Joseph Hasting
发明人： Deepak Mital , William Burroughs , David Sonnier , Steven Pollock , David Brown , Joseph Hasting
IPC分类号： G06F12/00
CPC分类号： G06F12/123 , G06F12/084 , H04L49/101 , H04L49/109 , H04L49/506
摘要： Described embodiments provide a network processor having a plurality of processing modules coupled to a system cache and a shared memory. A memory manager allocates blocks of the shared memory to a requesting one of the processing modules. The allocated blocks store data corresponding to packets received by the network processor. The memory manager maintains a reference count for each allocated memory block indicating a number of processing modules accessing the block. One of the processing modules reads the data stored in the allocated memory blocks, stores the read data to corresponding entries of the system cache and operates on the data stored in the system cache. Upon completion of operation on the data, the processing module requests to decrement the reference count of each memory block. Based on the reference count, the memory manager invalidates the entries of the system cache and deallocates the memory blocks.
摘要翻译：所描述的实施例提供具有耦合到系统高速缓存和共享存储器的多个处理模块的网络处理器。存储器管理器将共享存储器的块分配给请求的一个处理模块。所分配的块存储对应于由网络处理器接收的分组的数据。存储器管理器为每个分配的存储块维护指示接入该块的处理模块的数量的引用计数。其中一个处理模块读取存储在分配的存储器块中的数据，将读取的数据存储到系统高速缓存的相应条目，并对存储在系统高速缓存中的数据进行操作。在完成对数据的操作时，处理模块请求递减每个存储器块的引用计数。基于引用计数，内存管理器使系统缓存的条目无效，并释放内存块。

4. 发明申请

US20120131283A1 MEMORY MANAGER FOR A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE 有权
标题翻译：网络通信处理器架构的内存管理器
公开(公告)号：US20120131283A1
公开(公告)日：2012-05-24
申请号：US13359690
申请日：2012-01-27
申请人： Deepak Mital , William Burroughs , David Sonnier , Steven Pollock , David Brown , Joseph Hasting
发明人： Deepak Mital , William Burroughs , David Sonnier , Steven Pollock , David Brown , Joseph Hasting
IPC分类号： G06F12/08
CPC分类号： G06F12/123 , G06F12/084 , H04L49/101 , H04L49/109 , H04L49/506
摘要： Described embodiments provide a network processor having a plurality of processing modules coupled to a system cache and a shared memory. A memory manager allocates blocks of the shared memory to a requesting one of the processing modules. The allocated blocks store data corresponding to packets received by the network processor. The memory manager maintains a reference count for each allocated memory block indicating a number of processing modules accessing the block. One of the processing modules reads the data stored in the allocated memory blocks, stores the read data to corresponding entries of the system cache and operates on the data stored in the system cache. Upon completion of operation on the data, the processing module requests to decrement the reference count of each memory block. Based on the reference count, the memory manager invalidates the entries of the system cache and deallocates the memory blocks.
摘要翻译：所描述的实施例提供具有耦合到系统高速缓存和共享存储器的多个处理模块的网络处理器。存储器管理器将共享存储器的块分配给请求的一个处理模块。所分配的块存储对应于由网络处理器接收的分组的数据。存储器管理器为每个分配的存储块维护指示接入该块的处理模块的数量的引用计数。其中一个处理模块读取存储在分配的存储器块中的数据，将读取的数据存储到系统高速缓存的相应条目，并对存储在系统高速缓存中的数据进行操作。在完成对数据的操作时，处理模块请求递减每个存储器块的引用计数。基于引用计数，内存管理器使系统缓存的条目无效，并释放内存块。

5. 发明申请

US20070276850A1 Methods and apparatus for updating data structures during in-service upgrade of software in network processor 有权
标题翻译：网络处理器软件在线升级过程中更新数据结构的方法与装置
公开(公告)号：US20070276850A1
公开(公告)日：2007-11-29
申请号：US11412762
申请日：2006-04-27
申请人： Rajarshi Bhattacharya , David Sonnier , Narender Vangati
发明人： Rajarshi Bhattacharya , David Sonnier , Narender Vangati
IPC分类号： G06F7/00
CPC分类号： G06F8/656
摘要： Improved techniques are disclosed for performing an in-service upgrade of software associated with a network or packet processor. By way of example, a method of managing data structures associated with code executable on a packet processor includes the following steps. Data structures in the code are identified as being one of static data structures and non-static data structures, wherein a static data structure includes a data structure that is not changed during execution of the packet processor code and a non-static data structure includes a data structure that is changed during execution of the packet processor code. One or more data structures associated with the packet processor code are managed in a manner specific to the identification of the one or more data structures as static data structures or non-static data structures. At least a portion of the data structures may include tree structures.
摘要翻译：公开了用于执行与网络或分组处理器相关联的软件的在职升级的改进的技术。作为示例，管理与分组处理器上可执行的代码相关联的数据结构的方法包括以下步骤。代码中的数据结构被识别为静态数据结构和非静态数据结构之一，其中静态数据结构包括在分组处理器代码的执行期间不改变的数据结构，并且非静态数据结构包括数据结构在分组处理器代码执行期间发生变化。与分组处理器代码相关联的一个或多个数据结构以特定于一个或多个数据结构的标识作为静态数据结构或非静态数据结构的方式进行管理。数据结构的至少一部分可以包括树结构。

6. 发明申请

US20070255764A1 Methods and apparatus for performing in-service upgrade of software in network processor 有权
标题翻译：在网络处理器中执行软件在线升级的方法和装置
公开(公告)号：US20070255764A1
公开(公告)日：2007-11-01
申请号：US11412915
申请日：2006-04-27
申请人： David Sonnier , Narender Vangati
发明人： David Sonnier , Narender Vangati
IPC分类号： G06F17/30
CPC分类号： G06F8/656
摘要： Improved techniques are disclosed for performing an in-service upgrade of software associated with a network or packet processor. By way of example, a method of performing an in-service upgrade of code, storable in a memory associated with a packet processor and executable on the packet processor, from a first code version to a second code version, includes the following steps. A first step includes preparing for the upgrade by generating one or more write operations to effectuate the code upgrade from the first code version to the second code version. A second step includes updating the code from the first code version to the second code version by propagating the one or more write operations to the packet processor. A third step includes cleaning up after the updating step by reclaiming one or more memory locations available after the update step. As such, the storage of only a single version of the code in the memory associated with the packet processor is required.
摘要翻译：公开了用于执行与网络或分组处理器相关联的软件的在职升级的改进的技术。作为示例，执行可存储在与分组处理器相关联并且可在分组处理器上执行的存储器中的代码的从第一代码版本到第二代码版本的代码的在役升级的方法包括以下步骤。第一步包括通过生成一个或多个写入操作来准备升级，以实现从第一代码版本到第二代码版本的代码升级。第二步包括通过将一个或多个写入操作传播到分组处理器来将代码从第一代码版本更新为第二代码版本。第三步包括在更新步骤之后通过回收在更新步骤之后可用的一个或多个存储器位置进行清理。因此，仅需要在与分组处理器相关联的存储器中存储单个版本的代码。

7. 发明申请

US20060088040A1 Virtual segmentation system and method of operation thereof 有权
标题翻译：虚拟分割系统及其操作方法
公开(公告)号：US20060088040A1
公开(公告)日：2006-04-27
申请号：US11299645
申请日：2005-12-12
申请人： David Kramer , David Sonnier
发明人： David Kramer , David Sonnier
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L12/5601 , H04L49/90 , H04L49/9073 , H04L2012/5652 , H04L2012/5658 , H04L2012/5667 , H04L2012/5681
摘要： A virtual segmentation system and a method of operating the same. In one embodiment, the virtual segmentation system includes a protocol data unit receiver subsystem configured to (i) receive at least a portion of a protocol data unit and (ii) store the at least a portion of the protocol data unit in at least one block, and a virtual segmentation subsystem, associated with the protocol data unit receiver subsystem, configured to perform virtual segmentation on the protocol data unit by segmenting the at least one block when retrieved without reassembling an entirety of the protocol data unit.
摘要翻译：虚拟分割系统及其操作方法。在一个实施例中，虚拟分段系统包括协议数据单元接收器子系统，其被配置为（i）接收协议数据单元的至少一部分，以及（ii）将协议数据单元的至少一部分存储在至少一个块中以及与所述协议数据单元接收器子系统相关联的虚拟分段子系统，被配置为通过在未重新组合所述协议数据单元的整体的情况下分段所述至少一个块来对所述协议数据单元执行虚拟分段。

8. 发明申请

US20050223276A1 Method for encoding/decoding a binary signal state in a fault tolerant environment 有权
标题翻译：在容错环境中对二进制信号状态进行编码/解码的方法
公开(公告)号：US20050223276A1
公开(公告)日：2005-10-06
申请号：US11142562
申请日：2005-05-31
申请人： Hanan Moller , David Sonnier
发明人： Hanan Moller , David Sonnier
IPC分类号： G06F13/00 , G06F11/00 , G06K9/00 , H04L12/24 , H04L12/26
CPC分类号： H04L41/0663 , H04L43/0817
摘要： A method for use in a fault tolerant environment for assuring that devices within the environment switch between primary and back-up systems in response to remotely generated control signals. In one embodiment, the inventive system uses a binary code in the form of a pair of different frequency signals, i.e., a binary zero is represented by one frequency and a binary one is represented by another frequency. The signals may be continuous or may be sent in timed bursts. At the individual devices, such as the aforementioned line cards, a receiver is provided to detect the presence of the signals. Since the line cards already have receivers to detect the binary signal, modification to detect a frequency signal requires the addition of minimal components. The receiver also includes circuitry for reporting the status of the card and such circuitry can be used to report to the remote controller whether the signals are reaching the line card. Alternately, the signals could be sent in burst format using a single frequency in which the number of bursts could indicate a binary one or a binary zero. For example, if N bursts are received in some unit of time, that could be indicative of one binary state. If 2N burst are received in the same unit of time, that could be indicative of another binary state. In another form, the receiver could be programmed to look for N changes of frequency per unit of time to indicate one binary state and 2N changes of frequency could be indicative of another binary state.
摘要翻译：一种在容错环境中使用的方法，用于确保环境中的设备响应于远程产生的控制信号在主系统和备用系统之间切换。在一个实施例中，本发明的系统使用一对不同频率信号形式的二进制代码，即二进制零由一个频率表示，二进制代表由另一个频率表示。信号可以是连续的或可以以定时脉冲串发送。在诸如上述线卡的各个设备上，提供接收器来检测信号的存在。由于线路卡已经有接收机来检测二进制信号，因此要检测频率信号的修改需要添加最小的组件。接收器还包括用于报告卡的状态的电路，并且这种电路可用于向遥控器报告信号是否到达线路卡。或者，信号可以使用单个频率以突发格式发送，其中突发数可以指示二进制数或二进制零。例如，如果在某个时间单位接收到N个突发，则可以指示一个二进制状态。如果在相同的时间单位中接收到2N个突发，那可能表示另一个二进制状态。在另一种形式中，接收机可以被编程为寻找每单位时间的频率的N个变化，以指示一个二进制状态，并且2N个频率变化可以指示另一个二进制状态。

9. 发明申请

US20050111461A1 Processor with scheduler architecture supporting multiple distinct scheduling algorithms 有权
标题翻译：具有调度器架构的处理器，支持多种不同的调度算法
公开(公告)号：US20050111461A1
公开(公告)日：2005-05-26
申请号：US10722933
申请日：2003-11-26
申请人： Asif Khan , David Kramer , David Sonnier
发明人： Asif Khan , David Kramer , David Sonnier
IPC分类号： H04L12/56
CPC分类号： H04L47/2441 , H04L47/22 , H04L47/50 , H04L47/522 , H04L47/568 , H04L47/58 , H04L2012/5679
摘要： A processor includes a scheduler operative to schedule data blocks for transmission from a plurality of queues or other transmission elements, utilizing at least a first table and a second table. The first table may comprise at least first and second first-in first-out (FIFO) lists of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a first scheduling algorithm, such as a weighted fair queuing scheduling algorithm. The scheduler maintains a first table pointer identifying at least one of the first and second lists of the first table as having priority over the other of the first and second lists of the first table. The second table includes a plurality of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a second scheduling algorithm, such as a constant bit rate or variable bit rate scheduling algorithm. Association of a given one of the transmission elements with a particular one of the second table entries establishes a scheduling rate for that transmission element. The scheduler maintains a second table pointer identifying a current one of the second table entries that is eligible for transmission.
摘要翻译：处理器包括调度器，其利用至少第一表和第二表来调度用于从多个队列或其他传输元件传输的数据块。第一表可以包括对应于根据第一调度算法（例如加权公平排队调度算法）对数据块进行调度的传输元件的条目的至少第一和第二先进先出（FIFO）列表。调度器维护第一表指针，其将第一表的第一列表和第二列表中的至少一个列表标识为优先于第一表的第一和第二列表中的另一列。第二表包括对应于根据诸如恒定比特率或可变比特率调度算法的第二调度算法对其数据块进行调度的传输元件的多个条目。给定一个传输单元与特定的一个第二表项的关联建立该传输单元的调度速率。调度器维护第二表指针，其标识有资格传输的第二表条目中的当前一个。

10. 发明授权

US09195464B2 Tracking written addresses of a shared memory of a multi-core processor 有权
标题翻译：跟踪多核处理器的共享内存的写入地址
公开(公告)号：US09195464B2
公开(公告)日：2015-11-24
申请号：US13316145
申请日：2011-12-09
申请人： David Sonnier , Chris Randall Stone , Charles Edward Peet, Jr.
发明人： David Sonnier , Chris Randall Stone , Charles Edward Peet, Jr.
IPC分类号： G06F9/46 , G06F9/54 , G06F9/38 , H04L12/933 , H04L12/931 , G06F12/08
CPC分类号： G06F9/3834 , G06F12/0811 , G06F12/084 , G06F2212/301 , H04L49/101 , H04L49/109 , H04L49/506
摘要： Described embodiments provide a method of controlling processing flow in a network processor having one or more processing modules. A given one of the processing modules loads a script into a compute engine. The script includes instructions for the compute engine. The given one of the processing modules loads a register file into the compute engine. The register file includes operands for the instructions of the loaded script. A tracking vector of the compute engine is initialized to a default value, and the compute engine executes the instructions of the loaded script based on the operands of the loaded register file. The compute engine updates corresponding portions of the register file with updated data corresponding to the executed script. The tracking vector tracks the updated portions of the register file. The compute engine provides the tracking vector and the updated register file to the given one of the processing modules.
摘要翻译：所描述的实施例提供了一种控制具有一个或多个处理模块的网络处理器中的处理流程的方法。给定的一个处理模块将脚本加载到计算引擎中。该脚本包括计算引擎的说明。给定的一个处理模块将一个寄存器文件加载到计算引擎中。寄存器文件包括用于加载脚本的指令的操作数。计算引擎的跟踪向量被初始化为默认值，并且计算引擎基于加载的寄存器文件的操作数来执行加载脚本的指令。计算引擎使用对应于执行脚本的更新数据更新寄存器文件的相应部分。跟踪向量跟踪寄存器文件的更新部分。计算引擎将跟踪向量和更新的寄存器文件提供给给定的一个处理模块。

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