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1. 发明申请

US20090089514A1 Implementing Asynchronous Request for Forcing Dynamic Memory into Self Refresh 审中-公开
标题翻译：实现异步请求强制动态内存进入自刷新
公开(公告)号：US20090089514A1
公开(公告)日：2009-04-02
申请号：US11864738
申请日：2007-09-28
申请人： Durgesh Srivastava , Niall McDonnell , Will Akin , Mark Schmisseur
发明人： Durgesh Srivastava , Niall McDonnell , Will Akin , Mark Schmisseur
IPC分类号： G06F12/00
CPC分类号： G06F13/4234 , G06F1/30 , Y02D10/14 , Y02D10/151
摘要： In some embodiments a memory controller receives a signal indicating a power condition of a system. In response to the received signal the memory controller controls a clock enable signal to a memory, allows only already issued memory controller signals to finish, and forces the memory into a self refresh. A transition is made such that power is only provided to the memory controller and to the memory, and no power is provided to any other components in the system. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，存储器控制器接收指示系统的功率状况的信号。响应于接收到的信号，存储器控制器控制到存储器的时钟使能信号，仅允许已经发出的存储器控制器信号完成，并强制存储器进行自刷新。进行转换，使得仅向存储器控制器和存储器提供电力，并且不向系统中的任何其他组件提供电力。描述和要求保护其他实施例。

2. 发明授权

US09417821B2 Presentation of direct accessed storage under a logical drive model 有权
标题翻译：在逻辑驱动器模型下呈现直接访问存储
公开(公告)号：US09417821B2
公开(公告)日：2016-08-16
申请号：US13976262
申请日：2011-09-30
申请人： Thomas M. Slaight , Sivakumar Radhakrishnan , Mark Schmisseur , Pankaj Kumar , Saptarshi Mondal , Sin S. Tan , David C. Lee , Marc T. Jones , Geetani R. Edirisooriya , Bradley A. Burres , Brian M. Leitner , Kenneth C. Haren , Michael T. Klinglesmith , Matthew R. Wilcox , Eric J. Dahlen
发明人： Thomas M. Slaight , Sivakumar Radhakrishnan , Mark Schmisseur , Pankaj Kumar , Saptarshi Mondal , Sin S. Tan , David C. Lee , Marc T. Jones , Geetani R. Edirisooriya , Bradley A. Burres , Brian M. Leitner , Kenneth C. Haren , Michael T. Klinglesmith , Matthew R. Wilcox , Eric J. Dahlen
IPC分类号： G06F3/06 , G06F13/28 , G06F11/10 , G06F12/08
CPC分类号： G06F13/28 , G06F3/061 , G06F3/0613 , G06F3/0619 , G06F3/0626 , G06F3/064 , G06F3/0646 , G06F3/065 , G06F3/0659 , G06F3/0688 , G06F3/0689 , G06F11/1068 , G06F12/0866 , G06F13/102 , G06F13/1668 , G06F13/4068 , G06F13/4282 , G06F2212/262 , G06F2213/0026 , G06F2213/0032
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.
摘要翻译：根据本文公开的实施例，提供了用于在逻辑驱动器模型下呈现直接访问存储的方法，系统，机制，技术和装置; 实现用于协作NVM数据保护的分布式架构; 数据镜像，以保持一致的SSD延迟; 通过并发RAID处理来提升控制器的性能和支持DIF的RAS; 执行门铃机制的仲裁和资源计划，包括门铃仲裁以公平和防止冲突拥堵; 并且通过使用中断合并方案在控制器中实现使用消息传送单元和NTB的多个中断生成。

3. 发明申请

US20060168359A1 METHOD, SYSTEM, AND PROGRAM FOR HANDLING INPUT/OUTPUT COMMANDS 有权
标题翻译：用于处理输入/输出命令的方法，系统和程序
公开(公告)号：US20060168359A1
公开(公告)日：2006-07-27
申请号：US11279086
申请日：2006-04-07
申请人： Sailesh Bissessur , Richard Mackey , Mark Schmisseur , David Smith
发明人： Sailesh Bissessur , Richard Mackey , Mark Schmisseur , David Smith
IPC分类号： G06F3/00
CPC分类号： G06F13/28
摘要： Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.
摘要翻译：提供了一种用于处理输入/输出（I / O）请求的方法，系统和程序。总线使得能够与发起者，目标设备和设备控制器进行通信，其中设备控制器访问目标设备以执行指向目标设备的I / O命令。接收到I / O请求命令以访问目标设备。启动器被配置为将总线上的至少一个数据请求发送到设备控制器的预定义地址窗口中的一个存储器地址。设备控制器被允许从总线上的启动器向预定义的地址窗口中的存储器地址提出数据请求，以针对目标设备执行数据请求。

4. 发明申请

US20050060441A1 Multi-use data access descriptor 审中-公开
标题翻译：多用数据访问描述符
公开(公告)号：US20050060441A1
公开(公告)日：2005-03-17
申请号：US10882377
申请日：2004-06-30
申请人： Mark Schmisseur
发明人： Mark Schmisseur
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： Described are a system and method of processing data access descriptors. One or more data fields in a data access descriptor may be selectively processed as information identifying a memory location of a contiguous data buffer or information identifying a memory location of a scatter gather list based upon information in a control data field of the data access descriptor.
摘要翻译：描述了一种处理数据访问描述符的系统和方法。可以基于数据访问描述符的控制数据字段中的信息，有选择地处理数据访问描述符中的一个或多个数据字段作为识别连续数据缓冲器的存储器位置的信息或标识分散收集列表的存储器位置的信息。

5. 发明申请

US20060074960A1 Providing data integrity for data streams 有权
标题翻译：为数据流提供数据完整性
公开(公告)号：US20060074960A1
公开(公告)日：2006-04-06
申请号：US10946479
申请日：2004-09-20
申请人： Marc Goldschmidt , Robert Sheffield , Mark Schmisseur , Richard Beckett
发明人： Marc Goldschmidt , Robert Sheffield , Mark Schmisseur , Richard Beckett
IPC分类号： G06F7/00
CPC分类号： H03M13/11 , G06F2211/109 , H04L1/0065 , H04L1/0071
摘要： Provided are a method, system, and article of manufacture for providing data integrity for data streams. Input data streams are received. A parity data stream is generated by computing parity data from the input data streams, wherein the parity data stream comprises data blocks. Data integrity fields are computed for the data blocks, wherein a data integrity field is used to ensure the integrity of a data block for which the data integrity field is computed. The computed data integrity fields are added to the data blocks to generate an output stream.
摘要翻译：提供了一种用于为数据流提供数据完整性的方法，系统和制品。接收输入数据流。通过从输入数据流计算奇偶校验数据来生成奇偶校验数据流，其中奇偶校验数据流包括数据块。为数据块计算数据完整性字段，其中使用数据完整性字段来确保计算数据完整性字段的数据块的完整性。计算的数据完整性字段被添加到数据块以生成输出流。

6. 发明申请

US20050160307A1 Method, system, and program for generating parity data 有权
标题翻译：用于生成奇偶校验数据的方法，系统和程序
公开(公告)号：US20050160307A1
公开(公告)日：2005-07-21
申请号：US10747938
申请日：2003-12-29
申请人： Mark Schmisseur
发明人： Mark Schmisseur
IPC分类号： G06F3/06 , G06F11/00 , G06F11/10
CPC分类号： G06F11/1076
摘要： Provided are a method, system, and program for generating parity data when updating old data stored in an array of storage devices in a data organization type which utilizes parity data. In one embodiment, a logic engine has plural registers or store queues in which new data obtained in a read operation is stored. A logic function such as an Exclusive-OR function is performed on the new data in each of the plural registers using old data obtained in another read operation. A logic function such as an Exclusive-OR function is performed on the intermediate data in one of the plural registers using old parity data of a first type obtained in another read operation, to generate new parity data of the first type. A logic function such as an Exclusive-OR function is performed on the intermediate data in another of the plural registers using old parity data of a second type obtained in another read operation, to generate new parity data of the second type.
摘要翻译：提供了一种用于在更新存储在利用奇偶校验数据的数据组织类型的存储设备阵列中的旧数据时产生奇偶校验数据的方法，系统和程序。在一个实施例中，逻辑引擎具有多个寄存器或存储队列，其中存储在读取操作中获得的新数据。使用在另一读操作中获得的旧数据，对多个寄存器中的每个寄存器中的新数据执行诸如“异或”功能的逻辑功能。使用在另一读取操作中获得的第一类型的旧奇偶校验数据，对多个寄存器之一中的中间数据执行诸如“异或”功能的逻辑功能，以生成第一类型的新奇偶校验数据。使用在另一读取操作中获得的第二类型的旧奇偶校验数据对多个寄存器中的另一个寄存器中的另一个寄存器中的中间数据执行诸如“异或”功能的逻辑功能，以生成第二类型的新奇偶校验数据。

7. 发明申请

US20060156211A1 Method and system for syndrome generation and data recovery 有权
标题翻译：综合征发生和数据恢复的方法和系统
公开(公告)号：US20060156211A1
公开(公告)日：2006-07-13
申请号：US11021708
申请日：2004-12-23
申请人： Samantha Edirisooriya , Gregory Tse , Mark Schmisseur , Robert Sheffield
发明人： Samantha Edirisooriya , Gregory Tse , Mark Schmisseur , Robert Sheffield
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F11/1076 , G06F2211/1004 , G06F2211/1057
摘要： A method and system for syndrome generation and data recovery is described. The system includes a recovery device coupled to one or more storage devices to recover data in the storage devices. The recovery device includes a first comparator to generate a first parity factor based on data in one or more of the storage devices, a multiplier to multiply data from one or more of the storage devices with a multiplication factor to generate a product, and a second comparator coupled to the multiplier to generate a second parity factor based at least in part on the product.
摘要翻译：描述了一种用于综合征生成和数据恢复的方法和系统。该系统包括耦合到一个或多个存储设备以恢复存储设备中的数据的恢复设备。恢复装置包括：第一比较器，用于基于存储装置中的一个或多个中的数据产生第一奇偶校验因子;乘法器，用于将来自一个或多个存储装置的数据与乘法因子相乘以产生乘积;以及第二比较器比较器耦合到乘法器，以至少部分地基于产品来产生第二奇偶校验因子。

8. 发明申请

US20060047934A1 Integrated circuit capable of memory access control 审中-公开
标题翻译：具有内存访问控制的集成电路
公开(公告)号：US20060047934A1
公开(公告)日：2006-03-02
申请号：US10931278
申请日：2004-08-31
申请人： Mark Schmisseur , Joseph Murray , Richard Mackey , Micheil Lee
发明人： Mark Schmisseur , Joseph Murray , Richard Mackey , Micheil Lee
IPC分类号： G06F12/00
CPC分类号： G06F13/12
摘要： A method according to one embodiment may include selecting a port, among a plurality of ports. The method of this embodiment may also include selecting between a memory read request and a memory write request from at least one port, among the plurality of ports, based on, at least in part, at least one memory access rule. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：根据一个实施例的方法可以包括在多个端口之中选择端口。该实施例的方法还可以包括至少部分地基于至少一个存储器访问规则来选择在多个端口中的至少一个端口的存储器读请求和存储器写请求之间。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

9. 发明申请

US20050256990A1 Integrated circuit having processor and bridging capabilities 失效
标题翻译：集成电路具有处理器和桥接功能
公开(公告)号：US20050256990A1
公开(公告)日：2005-11-17
申请号：US10846459
申请日：2004-05-14
申请人： Mark Schmisseur , Deif Atallah
发明人： Mark Schmisseur , Deif Atallah
IPC分类号： G06F13/36 , G06F13/40
CPC分类号： G06F13/4027
摘要： An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a processor, a bridge, and circuitry capable of coupling the bridge and the processor to a first bus and to a second bus. The first bus may be compatible with a first bus protocol, the second bus may be compatible with a second bus protocol, and the first and second bus protocols may be different from each other. The bridge may be capable of, in response at least in part to a request from the processor, preventing a command received at the bridge via the first bus from being forwarded from the bridge to the second bus. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：根据一个实施例的装置可以包括集成电路。集成电路可以包括处理器，桥接器和能够将桥接器和处理器耦合到第一总线和第二总线的电路。第一总线可以与第一总线协议兼容，第二总线可以与第二总线协议兼容，并且第一和第二总线协议可以彼此不同。至少部分地响应于来自处理器的请求，桥可以能够阻止经由第一总线在桥接处接收的命令从桥接器转发到第二总线。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

10. 发明申请

US20050256977A1 Integrated circuit having processor and switch capabilities 审中-公开
标题翻译：具有处理器和开关功能的集成电路
公开(公告)号：US20050256977A1
公开(公告)日：2005-11-17
申请号：US10846458
申请日：2004-05-14
申请人： Eric Dehaemer , Mark Schmisseur , Deif Atallah
发明人： Eric Dehaemer , Mark Schmisseur , Deif Atallah
IPC分类号： G06F13/16 , G06F13/40 , G06F13/14
CPC分类号： G06F13/1684 , G06F13/4022
摘要： An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a processor and a switch. The switch may include at least one port capable of being coupled to at least one external communication link. The processor may be capable of issuing a request to the switch to request that the switch block forwarding via the at least one port of a command received by the switch. The switch may be capable of issuing to an issuer of the command, in response at least in part to receipt by the switch of the command, a response indicating absence of the at least one port from the switch. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：根据一个实施例的装置可以包括集成电路。集成电路可以包括处理器和开关。交换机可以包括能够被耦合到至少一个外部通信链路的至少一个端口。处理器可以能够向交换机发出请求，以请求交换机通过至少一个端口转发由交换机接收的命令。所述交换机可以能够至少部分地向所述交换机接收到所述命令的颁发者颁发指示所述至少一个端口不存在于所述交换机的响应。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

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