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1. 发明申请

US20110243289A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20110243289A1
公开(公告)日：2011-10-06
申请号：US13050277
申请日：2011-03-17
申请人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Kwang-Il Park , Seung-Jun Bae
发明人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Kwang-Il Park , Seung-Jun Bae
IPC分类号： H04L7/04
CPC分类号： G11C7/22 , G11C7/04 , G11C7/222 , G11C2207/2254
摘要： A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal; determining one of the data pins to be a representative pin; performing clock and data recovery (CDR) on read data of the representative pin; and adjusting a phase of the data clock signal based on the CDR.
摘要翻译：一种对时钟信号的相位进行调谐的方法包括：与数据时钟信号同步地对输入和输出数据的多个数据引脚进行数据训练; 确定一个数据引脚作为代表性引脚; 在代表引脚的读取数据上执行时钟和数据恢复（CDR）; 以及基于所述CDR调整所述数据时钟信号的相位。

2. 发明授权

US08649238B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08649238B2
公开(公告)日：2014-02-11
申请号：US13078218
申请日：2011-04-01
申请人： Dong-Min Kim , Young-Soo Sohn , Seung-Jun Bae , Kwang-Il Park
发明人： Dong-Min Kim , Young-Soo Sohn , Seung-Jun Bae , Kwang-Il Park
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C8/18
摘要： A semiconductor memory device includes a memory cell array, an address control unit and a logic circuit. The memory cell array includes a plurality of banks which are divided into a first bank block and a second bank block. The address control unit accesses the memory cell array. The logic circuit controls the address control unit based on a command and an address signal such that the first and second bank blocks commonly operate in a first operation mode, and the first and second bank blocks individually operate in a second operation mode.
摘要翻译：半导体存储器件包括存储单元阵列，地址控制单元和逻辑电路。存储单元阵列包括被划分成第一存储块和第二存储块的多个存储体。地址控制单元访问存储单元阵列。逻辑电路基于命令和地址信号控制地址控制单元，使得第一和第二存储体块以第一操作模式共同操作，并且第一和第二存储体块以第二操作模式分别操作。

3. 发明授权

US08531898B2 On-die termination circuit, data output buffer and semiconductor memory device 有权
标题翻译：片上终端电路，数据输出缓冲器和半导体存储器件
公开(公告)号：US08531898B2
公开(公告)日：2013-09-10
申请号：US13048219
申请日：2011-03-15
申请人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Jin-Il Lee , Kwang-Il Park , Seung-Jun Bae , Sang-Hyup Kwak
发明人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Jin-Il Lee , Kwang-Il Park , Seung-Jun Bae , Sang-Hyup Kwak
IPC分类号： G11C7/00
CPC分类号： H03K19/018585 , G06F2213/0038 , G11C5/063 , G11C7/1051 , G11C7/1057 , H04L25/0278 , H04L25/028 , H04L25/0292
摘要： An on-die termination circuit includes a termination resistor unit connected to an external pin, and a termination control unit connected to the termination resistor unit. The termination resistor unit provides termination impedance to a transmission line connected to the external pin. The termination control unit varies the termination impedance in response to a plurality of bits of strength code associated with a data rate.
摘要翻译：片上终端电路包括连接到外部引脚的终端电阻单元和连接到终端电阻单元的终端控制单元。终端电阻单元为连接到外部引脚的传输线提供终端阻抗。终端控制单元响应于与数据速率相关联的多个强度码位改变终端阻抗。

4. 发明授权

US08631266B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08631266B2
公开(公告)日：2014-01-14
申请号：US13050277
申请日：2011-03-17
申请人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Kwang-Il Park , Seung-Jun Bae
发明人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Kwang-Il Park , Seung-Jun Bae
IPC分类号： H04L7/04
CPC分类号： G11C7/22 , G11C7/04 , G11C7/222 , G11C2207/2254
摘要： A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal; determining one of the data pins to be a representative pin; performing clock and data recovery (CDR) on read data of the representative pin; and adjusting a phase of the data clock signal based on the CDR.
摘要翻译：一种对时钟信号的相位进行调谐的方法包括：与数据时钟信号同步地对输入和输出数据的多个数据引脚进行数据训练; 确定一个数据引脚作为代表性引脚; 在代表引脚的读取数据上执行时钟和数据恢复（CDR）; 以及基于所述CDR调整所述数据时钟信号的相位。

5. 发明申请

US20110242916A1 ON-DIE TERMINATION CIRCUIT, DATA OUTPUT BUFFER AND SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：接通终端电路，数据输出缓冲器和半导体存储器件
公开(公告)号：US20110242916A1
公开(公告)日：2011-10-06
申请号：US13048219
申请日：2011-03-15
申请人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Jin-Il Lee , Kwang-II Park , Seung-Jun Bae , Sang-Hyup Kwak
发明人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Jin-Il Lee , Kwang-II Park , Seung-Jun Bae , Sang-Hyup Kwak
IPC分类号： G11C7/00 , H03K19/003
CPC分类号： H03K19/018585 , G06F2213/0038 , G11C5/063 , G11C7/1051 , G11C7/1057 , H04L25/0278 , H04L25/028 , H04L25/0292
摘要： An on-die termination circuit includes a termination resistor unit connected to an external pin, and a termination control unit connected to the termination resistor unit. The termination resistor unit provides termination impedance to a transmission line connected to the external pin. The termination control unit varies the termination impedance in response to a plurality of bits of strength code associated with a data rate.
摘要翻译：片上终端电路包括连接到外部引脚的终端电阻单元和连接到终端电阻单元的终端控制单元。终端电阻单元为连接到外部引脚的传输线提供终端阻抗。终端控制单元响应于与数据速率相关联的多个强度码位改变终端阻抗。

6. 发明申请

US20190138473A1 SEMICONDUCTOR DEVICES INCLUDING COMMAND PRIORITY POLICY MANAGEMENT AND RELATED SYSTEMS 审中-公开
公开(公告)号：US20190138473A1
公开(公告)日：2019-05-09
申请号：US16005063
申请日：2018-06-11
申请人： Dong-Min Kim , Jeong-woo Park , Wook Han Jeong , Jin Hwan Choi
发明人： Dong-Min Kim , Jeong-woo Park , Wook Han Jeong , Jin Hwan Choi
IPC分类号： G06F13/26 , G06F13/10
CPC分类号： G06F13/26 , G06F13/102
摘要： Provided is a semiconductor device and a semiconductor system. A semiconductor device can include a command priority policy manager circuit which generates command priority policy information including a command priority compliance policy for a command directed to a device. A host interface circuit, can be coupled to the command priority policy manager circuit to receive the command priority policy information from the command priority policy manager circuit, where the host interface circuit operable to transmit the command priority policy information via an electrical interface to the device.

7. 发明授权

US09036406B2 Magneto-resistive memory device including source line voltage generator 有权
标题翻译：磁阻存储器件包括源极线电压发生器
公开(公告)号：US09036406B2
公开(公告)日：2015-05-19
申请号：US13832101
申请日：2013-03-15
申请人： Hye-Jin Kim , Sang-Kyu Kang , Dong-Hyun Sohn , Dong-Min Kim , Kyu-Chan Lee
发明人： Hye-Jin Kim , Sang-Kyu Kang , Dong-Hyun Sohn , Dong-Min Kim , Kyu-Chan Lee
IPC分类号： G11C11/00 , G11C11/16 , G11C5/14
CPC分类号： G11C11/1675 , G11C5/147 , G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1697
摘要： A MRAM includes a memory cell array of spin-transfer torque magnetic random access memory (STT-MRAM) cells and a source line commonly connected to the plurality of STT-MRAM cells. A source line voltage generator generates a source line driving voltage in response to an external power supply voltage and provides the source line driving voltage to the source line.
摘要翻译： MRAM包括自旋转移转矩磁随机存取存储器（STT-MRAM）单元的存储单元阵列和通常连接到多个STT-MRAM单元的源极线。源极线电压发生器响应于外部电源电压产生源极线驱动电压，并将源极线驱动电压提供给源极线。

8. 发明授权

US08548092B2 Method and apparatus for reducing peak to average power ratio using peak windowing 有权
标题翻译：使用峰值窗口降低峰均功率比的方法和装置
公开(公告)号：US08548092B2
公开(公告)日：2013-10-01
申请号：US13004271
申请日：2011-01-11
申请人： In-Tae Kang , Jung-Hwa Bae , Jung-Uk Woo , Shin-Ho Kim , Sang-Min Bae , Jong-Han Lim , Dong-Min Kim , Bo-Rham Lee
发明人： In-Tae Kang , Jung-Hwa Bae , Jung-Uk Woo , Shin-Ho Kim , Sang-Min Bae , Jong-Han Lim , Dong-Min Kim , Bo-Rham Lee
IPC分类号： H04K1/02
CPC分类号： H04L27/2624
摘要： A method and apparatus for reducing a Peak to Average Power Ratio (PAPR) using peak windowing is provided. In the apparatus, an absolute value calculator calculates an absolute value of an input signal, a subtractor subtracts a predetermined clipping threshold level from the absolute value, a smoothing unit performs smoothing on the subtracted signal according to a predetermined smoothing scheme and outputs a first smoothed signal, an adder adds the first smoothed signal to the clipping threshold level, an inverse calculator outputs a second smoothed signal by multiplying the clipping threshold level by an inverse of the added signal, and a multiplier outputs a final PAPR-reduced signal by multiplying the input signal by the second smoothed signal. The method and apparatus address an overcompensation problem while processing signals having a large bandwidth and a high data rate without delay, thereby minimizing the clipping influences on Bit Error Rate (BER) and Adjacent Channel Leakage Ratio (ACLR) performances.
摘要翻译：提供了一种使用峰值窗口降低峰均功率比（PAPR）的方法和装置。在设备中，绝对值计算器计算输入信号的绝对值，减法器根据绝对值减去预定的限幅阈值电平，平滑单元根据预定的平滑方案对减法信号进行平滑处理，并输出第一个平滑信号，加法器将第一平滑信号与削波阈值电平相加，逆计算器通过将削波阈值电平乘以相加信号的倒数来输出第二平滑信号，乘法器将最终的PAPR降低信号乘以输入信号由第二平滑信号。该方法和装置在不延迟地处理具有大带宽和高数据速率的信号的同时解决过度补偿问题，从而最小化对误码率（BER）和相邻信道泄漏比（ACLR）性能的削波影响。

9. 发明申请

US20100272052A1 APPARATUS AND METHOD FOR RANDOM ACCESS BASED ON CALL PRIORITY IN A MOBILE COMMUNICATION SYSTEM 有权
标题翻译：基于移动通信系统中的优先级的随机访问的装置和方法
公开(公告)号：US20100272052A1
公开(公告)日：2010-10-28
申请号：US12808083
申请日：2008-12-01
申请人： Dong-Min Kim , Young-Sung Kho
发明人： Dong-Min Kim , Young-Sung Kho
IPC分类号： H04W72/04
CPC分类号： H04W74/008 , H04W72/02 , H04W72/10 , H04W74/0833
摘要： An apparatus and method for random access based on call priority in a mobile communication system are provided, in which upon generation of a high-priority call, a mobile station selects a predetermined Random Access (RA) code indicating generation of a high-priority call, generates a preamble using the selected RA code, and transmits the preamble to a base station.
摘要翻译：提供一种基于移动通信系统中的呼叫优先级的随机接入的装置和方法，其中，在生成高优先级呼叫时，移动台选择指示生成高优先级呼叫的预定随机接入（RA）码使用所选择的RA代码生成前同步码，并将前导码发送到基站。

10. 发明申请

US20070009833A1 Photoresist composition, method for forming film pattern using the same, and method for manufacturing thin film transistor array panel using the same 有权
公开(公告)号：US20070009833A1
公开(公告)日：2007-01-11
申请号：US11483794
申请日：2006-07-07
申请人： Jeong-Min Park , Hi-Kuk Lee , Jin-Ho Ju , Woo-Seok Jeon , Doo-Hee Jung , Dong-Min Kim , Ki-Sik Choi
发明人： Jeong-Min Park , Hi-Kuk Lee , Jin-Ho Ju , Woo-Seok Jeon , Doo-Hee Jung , Dong-Min Kim , Ki-Sik Choi
IPC分类号： G03C1/00
CPC分类号： G03F7/022 , G03F7/0045
摘要： A photoresist composition, a method for forming a film pattern using the photoresist composition, and a method for manufacturing a thin film transistor array panel using the photoresist composition are provided. In one embodiment, a photoresist composition includes an alkali-soluble resin, a photosensitive compound, and an additive, for advantageously providing a uniform photoresist in a channel region.

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