专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08631266B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08631266B2
公开(公告)日：2014-01-14
申请号：US13050277
申请日：2011-03-17
申请人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Kwang-Il Park , Seung-Jun Bae
发明人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Kwang-Il Park , Seung-Jun Bae
IPC分类号： H04L7/04
CPC分类号： G11C7/22 , G11C7/04 , G11C7/222 , G11C2207/2254
摘要： A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal; determining one of the data pins to be a representative pin; performing clock and data recovery (CDR) on read data of the representative pin; and adjusting a phase of the data clock signal based on the CDR.
摘要翻译：一种对时钟信号的相位进行调谐的方法包括：与数据时钟信号同步地对输入和输出数据的多个数据引脚进行数据训练; 确定一个数据引脚作为代表性引脚; 在代表引脚的读取数据上执行时钟和数据恢复（CDR）; 以及基于所述CDR调整所述数据时钟信号的相位。

2. 发明授权

US08649238B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08649238B2
公开(公告)日：2014-02-11
申请号：US13078218
申请日：2011-04-01
申请人： Dong-Min Kim , Young-Soo Sohn , Seung-Jun Bae , Kwang-Il Park
发明人： Dong-Min Kim , Young-Soo Sohn , Seung-Jun Bae , Kwang-Il Park
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C8/18
摘要： A semiconductor memory device includes a memory cell array, an address control unit and a logic circuit. The memory cell array includes a plurality of banks which are divided into a first bank block and a second bank block. The address control unit accesses the memory cell array. The logic circuit controls the address control unit based on a command and an address signal such that the first and second bank blocks commonly operate in a first operation mode, and the first and second bank blocks individually operate in a second operation mode.
摘要翻译：半导体存储器件包括存储单元阵列，地址控制单元和逻辑电路。存储单元阵列包括被划分成第一存储块和第二存储块的多个存储体。地址控制单元访问存储单元阵列。逻辑电路基于命令和地址信号控制地址控制单元，使得第一和第二存储体块以第一操作模式共同操作，并且第一和第二存储体块以第二操作模式分别操作。

3. 发明授权

US08531898B2 On-die termination circuit, data output buffer and semiconductor memory device 有权
标题翻译：片上终端电路，数据输出缓冲器和半导体存储器件
公开(公告)号：US08531898B2
公开(公告)日：2013-09-10
申请号：US13048219
申请日：2011-03-15
申请人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Jin-Il Lee , Kwang-Il Park , Seung-Jun Bae , Sang-Hyup Kwak
发明人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Jin-Il Lee , Kwang-Il Park , Seung-Jun Bae , Sang-Hyup Kwak
IPC分类号： G11C7/00
CPC分类号： H03K19/018585 , G06F2213/0038 , G11C5/063 , G11C7/1051 , G11C7/1057 , H04L25/0278 , H04L25/028 , H04L25/0292
摘要： An on-die termination circuit includes a termination resistor unit connected to an external pin, and a termination control unit connected to the termination resistor unit. The termination resistor unit provides termination impedance to a transmission line connected to the external pin. The termination control unit varies the termination impedance in response to a plurality of bits of strength code associated with a data rate.
摘要翻译：片上终端电路包括连接到外部引脚的终端电阻单元和连接到终端电阻单元的终端控制单元。终端电阻单元为连接到外部引脚的传输线提供终端阻抗。终端控制单元响应于与数据速率相关联的多个强度码位改变终端阻抗。

4. 发明申请

US20110243289A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20110243289A1
公开(公告)日：2011-10-06
申请号：US13050277
申请日：2011-03-17
申请人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Kwang-Il Park , Seung-Jun Bae
发明人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Kwang-Il Park , Seung-Jun Bae
IPC分类号： H04L7/04
CPC分类号： G11C7/22 , G11C7/04 , G11C7/222 , G11C2207/2254
摘要： A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal; determining one of the data pins to be a representative pin; performing clock and data recovery (CDR) on read data of the representative pin; and adjusting a phase of the data clock signal based on the CDR.
摘要翻译：一种对时钟信号的相位进行调谐的方法包括：与数据时钟信号同步地对输入和输出数据的多个数据引脚进行数据训练; 确定一个数据引脚作为代表性引脚; 在代表引脚的读取数据上执行时钟和数据恢复（CDR）; 以及基于所述CDR调整所述数据时钟信号的相位。

5. 发明授权

US08654593B2 Stacked semiconductor memory device, memory system including the same, and method of repairing defects of through silicon vias 有权
标题翻译：堆叠的半导体存储器件，包括其的存储器系统以及通过硅通孔修复缺陷的方法
公开(公告)号：US08654593B2
公开(公告)日：2014-02-18
申请号：US13085776
申请日：2011-04-13
申请人： Tae-Young Oh , Kwang-Il Park , Yun-Seok Yang , Young-Soo Sohn , Si-Hong Kim , Seung-Jun Bae
发明人： Tae-Young Oh , Kwang-Il Park , Yun-Seok Yang , Young-Soo Sohn , Si-Hong Kim , Seung-Jun Bae
IPC分类号： G11C7/10
CPC分类号： G11C29/702 , G11C7/10 , H01L22/22 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06541
摘要： A stacked semiconductor memory device according to the inventive concepts may include a plurality of memory chips stacked above a processor chip, a plurality of TSVs, and I/O buffers. The TSVs may pass through the memory chips and are connected to the processor chip. I/O buffers may be coupled between all or part of the memory chips and the TSVs and may be selectively activated on the basis of defective states of the TSVs.
摘要翻译：根据本发明构思的叠层半导体存储器件可以包括堆叠在处理器芯片上方的多个存储器芯片，多个TSV和I / O缓冲器。 TSV可以通过存储器芯片并且连接到处理器芯片。 I / O缓冲器可以耦合在所有或部分存储器芯片和TSV之间，并且可以基于TSV的故障状态来选择性地激活。

6. 发明授权

US08254201B2 Semiconductor memory device having power-saving effect 有权
标题翻译：具有省电效果的半导体存储器件
公开(公告)号：US08254201B2
公开(公告)日：2012-08-28
申请号：US12797791
申请日：2010-06-10
申请人： Young-Soo Sohn , Kwang-Il Park , Kyoung-Ho Kim , Seung-Jun Bae
发明人： Young-Soo Sohn , Kwang-Il Park , Kyoung-Ho Kim , Seung-Jun Bae
IPC分类号： G11C8/18 , G11C7/10
CPC分类号： G11C7/22 , G11C7/1078 , G11C7/1084 , G11C8/18 , G11C2207/2227 , G11C2207/2272
摘要： A semiconductor memory device includes a memory cell array, a controller, and a data input/output (I/O) unit. The memory cell array includes a plurality of memory cells and is configured to store data. The controller is configured to enable a write clock signal in response to an active command when a write latency of the semiconductor device is less than a reference write latency and disable the write clock signal during a disabling period in which read data is output from the semiconductor device. The data I/O unit is configured to receive data in response to the write clock signal and output the data to the memory cell array.
摘要翻译：半导体存储器件包括存储单元阵列，控制器和数据输入/输出（I / O）单元。存储单元阵列包括多个存储单元，并被配置为存储数据。当半导体器件的写入延迟小于参考写入延迟并且在从半导体输出读取数据的禁用期间禁止写入时钟信号时，控制器被配置为响应于有效命令来使能写入时钟信号设备。数据I / O单元被配置为响应于写时钟信号接收数据并将数据输出到存储单元阵列。

7. 发明申请

US20110246857A1 MEMORY SYSTEM AND METHOD 审中-公开
标题翻译：记忆系统和方法
公开(公告)号：US20110246857A1
公开(公告)日：2011-10-06
申请号：US13078364
申请日：2011-04-01
申请人： Seung-Jun Bae , Kwang-Il Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
发明人： Seung-Jun Bae , Kwang-Il Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
IPC分类号： H03M13/09 , H03M13/05 , G06F11/10
CPC分类号： G06F11/1004 , H03M13/09
摘要： A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.
摘要翻译：存储器系统包括存储器控制器和存储器件。存储器件通过第一通道与存储器控制器交换数据，通过与存储器控制器的第二通道交换与数据相关联的第一循环冗余校验（CRC）代码，并且接收包括相关联的第二CRC码的命令/地址分组具有来自存储器控制器的命令/地址通过第三通道。

8. 发明授权

US07817494B2 Integrated circuit memory devices having internal command generators therein that support extended command sets using independent and dependent commands 有权
标题翻译：其中具有内部命令发生器的集成电路存储器件支持使用独立和相关命令的扩展命令集
公开(公告)号：US07817494B2
公开(公告)日：2010-10-19
申请号：US12236978
申请日：2008-09-24
申请人： Young-soo Sohn , Kwang-Il Park , Seung-Jun Bae
发明人： Young-soo Sohn , Kwang-Il Park , Seung-Jun Bae
IPC分类号： G11C11/00
CPC分类号： G11C11/4076 , G11C7/1006 , G11C7/1072 , G11C7/22 , G11C8/18
摘要： Integrated circuit memory devices include an internal command generator and a memory control circuit responsive to an internal command generated by the internal command generator. The internal command generator is configured to generate an internal command in response to a combination of an independent command and at least one dependent command received in sequence by the memory device. For example, the internal command generator may be configured to require the independent command to follow the at least one dependent command in the sequence when generating the internal command from the combination of the independent and dependent commands. Alternatively, the internal command generator may be configured to require the independent command to precede the at least one dependent command in the sequence before generating the internal command from the combination of the independent and dependent commands. These independent and dependent commands may be received by the memory device as respective multi-bit external command signals.
摘要翻译：集成电路存储器件包括响应于由内部命令发生器产生的内部命令的内部命令发生器和存储器控制电路。内部命令生成器被配置为响应于独立命令和由存储器装置依次接收的至少一个依赖命令的组合来生成内部命令。例如，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令时，要求独立命令遵循序列中的至少一个从属命令。或者，内部命令生成器可以被配置为在从独立命令和从属命令的组合生成内部命令之前，要求独立命令在序列中的至少一个从属命令之前。这些独立和依赖的命令可以被存储器装置接收为相应的多位外部命令信号。

9. 发明授权

US08593901B2 Data write training method 有权
标题翻译：数据写入训练方法
公开(公告)号：US08593901B2
公开(公告)日：2013-11-26
申请号：US13868425
申请日：2013-04-23
申请人： Tae-Young Oh , Young-Soo Sohn , Seung-Jun Bae , Kwang-Il Park
发明人： Tae-Young Oh , Young-Soo Sohn , Seung-Jun Bae , Kwang-Il Park
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1087 , G11C7/1093 , G11C2207/2254
摘要： Embodiments may be directed to a method of operating a semiconductor device, the method including receiving a first write training command, receiving a first write data responsive to the first write training command through a first data line, and transmitting the first write data through a second data line. Transmitting the first write data is performed without an additional training command.
摘要翻译：实施例可以涉及一种操作半导体器件的方法，所述方法包括接收第一写入训练命令，响应于通过第一数据线的第一写入训练命令接收第一写入数据，以及通过第二数据线发送第一写入数据数据线。在不附加训练命令的情况下执行发送第一写入数据。

10. 发明申请

US20110292742A1 Stacked Semiconductor Memory Device, Memory System Including The Same, And Method Of Repairing Defects Of Through Silicon Vias 有权
标题翻译：堆叠的半导体存储器件，包括其的存储器系统以及修复通孔硅缺陷的方法
公开(公告)号：US20110292742A1
公开(公告)日：2011-12-01
申请号：US13085776
申请日：2011-04-13
申请人： Tae-Young Oh , Kwang-il Park , Yun-Seok Yang , Young-Soo Sohn , Si-Hong Kim , Seung-Jun Bae
发明人： Tae-Young Oh , Kwang-il Park , Yun-Seok Yang , Young-Soo Sohn , Si-Hong Kim , Seung-Jun Bae
IPC分类号： G11C7/10 , H01L23/48
CPC分类号： G11C29/702 , G11C7/10 , H01L22/22 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06541
摘要： A stacked semiconductor memory device according to the inventive concepts may include a plurality of memory chips stacked above a processor chip, a plurality of TSVs, and I/O buffers. The TSVs may pass through the memory chips and are connected to the processor chip. I/O buffers may be coupled between all or part of the memory chips and the TSVs and may be selectively activated on the basis of defective states of the TSVs.
摘要翻译：根据本发明构思的叠层半导体存储器件可以包括堆叠在处理器芯片上方的多个存储器芯片，多个TSV和I / O缓冲器。 TSV可以通过存储器芯片并且连接到处理器芯片。 I / O缓冲器可以耦合在所有或部分存储器芯片和TSV之间，并且可以基于TSV的故障状态来选择性地激活。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式