专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08531898B2 On-die termination circuit, data output buffer and semiconductor memory device 有权
标题翻译：片上终端电路，数据输出缓冲器和半导体存储器件
公开(公告)号：US08531898B2
公开(公告)日：2013-09-10
申请号：US13048219
申请日：2011-03-15
申请人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Jin-Il Lee , Kwang-Il Park , Seung-Jun Bae , Sang-Hyup Kwak
发明人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Jin-Il Lee , Kwang-Il Park , Seung-Jun Bae , Sang-Hyup Kwak
IPC分类号： G11C7/00
CPC分类号： H03K19/018585 , G06F2213/0038 , G11C5/063 , G11C7/1051 , G11C7/1057 , H04L25/0278 , H04L25/028 , H04L25/0292
摘要： An on-die termination circuit includes a termination resistor unit connected to an external pin, and a termination control unit connected to the termination resistor unit. The termination resistor unit provides termination impedance to a transmission line connected to the external pin. The termination control unit varies the termination impedance in response to a plurality of bits of strength code associated with a data rate.
摘要翻译：片上终端电路包括连接到外部引脚的终端电阻单元和连接到终端电阻单元的终端控制单元。终端电阻单元为连接到外部引脚的传输线提供终端阻抗。终端控制单元响应于与数据速率相关联的多个强度码位改变终端阻抗。

2. 发明申请

US20110242916A1 ON-DIE TERMINATION CIRCUIT, DATA OUTPUT BUFFER AND SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：接通终端电路，数据输出缓冲器和半导体存储器件
公开(公告)号：US20110242916A1
公开(公告)日：2011-10-06
申请号：US13048219
申请日：2011-03-15
申请人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Jin-Il Lee , Kwang-II Park , Seung-Jun Bae , Sang-Hyup Kwak
发明人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Jin-Il Lee , Kwang-II Park , Seung-Jun Bae , Sang-Hyup Kwak
IPC分类号： G11C7/00 , H03K19/003
CPC分类号： H03K19/018585 , G06F2213/0038 , G11C5/063 , G11C7/1051 , G11C7/1057 , H04L25/0278 , H04L25/028 , H04L25/0292
摘要： An on-die termination circuit includes a termination resistor unit connected to an external pin, and a termination control unit connected to the termination resistor unit. The termination resistor unit provides termination impedance to a transmission line connected to the external pin. The termination control unit varies the termination impedance in response to a plurality of bits of strength code associated with a data rate.
摘要翻译：片上终端电路包括连接到外部引脚的终端电阻单元和连接到终端电阻单元的终端控制单元。终端电阻单元为连接到外部引脚的传输线提供终端阻抗。终端控制单元响应于与数据速率相关联的多个强度码位改变终端阻抗。

3. 发明申请

US20110243289A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20110243289A1
公开(公告)日：2011-10-06
申请号：US13050277
申请日：2011-03-17
申请人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Kwang-Il Park , Seung-Jun Bae
发明人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Kwang-Il Park , Seung-Jun Bae
IPC分类号： H04L7/04
CPC分类号： G11C7/22 , G11C7/04 , G11C7/222 , G11C2207/2254
摘要： A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal; determining one of the data pins to be a representative pin; performing clock and data recovery (CDR) on read data of the representative pin; and adjusting a phase of the data clock signal based on the CDR.
摘要翻译：一种对时钟信号的相位进行调谐的方法包括：与数据时钟信号同步地对输入和输出数据的多个数据引脚进行数据训练; 确定一个数据引脚作为代表性引脚; 在代表引脚的读取数据上执行时钟和数据恢复（CDR）; 以及基于所述CDR调整所述数据时钟信号的相位。

4. 发明授权

US08631266B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08631266B2
公开(公告)日：2014-01-14
申请号：US13050277
申请日：2011-03-17
申请人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Kwang-Il Park , Seung-Jun Bae
发明人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Kwang-Il Park , Seung-Jun Bae
IPC分类号： H04L7/04
CPC分类号： G11C7/22 , G11C7/04 , G11C7/222 , G11C2207/2254
摘要： A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal; determining one of the data pins to be a representative pin; performing clock and data recovery (CDR) on read data of the representative pin; and adjusting a phase of the data clock signal based on the CDR.
摘要翻译：一种对时钟信号的相位进行调谐的方法包括：与数据时钟信号同步地对输入和输出数据的多个数据引脚进行数据训练; 确定一个数据引脚作为代表性引脚; 在代表引脚的读取数据上执行时钟和数据恢复（CDR）; 以及基于所述CDR调整所述数据时钟信号的相位。

5. 发明申请

US20110310659A1 VOLTAGE-CONTROLLED OSCILLATOR AND PHASE-LOCKED LOOP CIRCUIT 有权
标题翻译：电压控制振荡器和相位锁定环路
公开(公告)号：US20110310659A1
公开(公告)日：2011-12-22
申请号：US13109157
申请日：2011-05-17
申请人： Ho-Seok Seol , Seung-Jun Bae , Sang-Hyup Kwak
发明人： Ho-Seok Seol , Seung-Jun Bae , Sang-Hyup Kwak
IPC分类号： G11C11/24 , H03B5/12 , H03B7/06
CPC分类号： H03B5/1228 , G11C7/222 , H03B5/1215 , H03B5/124
摘要： A voltage-controlled oscillator includes an oscillating unit configured to output first and second output clock signals at first and second nodes, respectively, the first and second output clock signals having a frequency that is variable in response to a control voltage. An active element unit connected to the oscillating unit is configured to maintain oscillation of the oscillating unit. A bias current generating unit connected to the active element unit at a bias node provides a bias current to the bias node and is adapted to adjust the bias current in response to a control code. First and second capacitor blocks connected to the oscillating unit and the active element unit provide first and second load capacitances, respectively, to the first and second nodes, respectively, in response to the control code.
摘要翻译：压控振荡器包括：振荡单元，被配置为分别在第一和第二节点处输出第一和第二输出时钟信号，第一和第二输出时钟信号具有响应于控制电压而变化的频率。连接到振荡单元的有源元件单元被配置为保持振荡单元的振荡。在偏置节点处连接到有源元件单元的偏置电流产生单元向偏置节点提供偏置电流，并且适于响应于控制代码调整偏置电流。连接到振荡单元和有源元件单元的第一和第二电容器块分别响应于控制代码分别向第一和第二节点提供第一和第二负载电容。

6. 发明授权

US08400818B2 Voltage-controlled oscillator and phase-locked loop circuit 有权
标题翻译：压控振荡器和锁相环电路
公开(公告)号：US08400818B2
公开(公告)日：2013-03-19
申请号：US13109157
申请日：2011-05-17
申请人： Ho-Seok Seol , Seung-Jun Bae , Sang-Hyup Kwak
发明人： Ho-Seok Seol , Seung-Jun Bae , Sang-Hyup Kwak
IPC分类号： G11C7/00
CPC分类号： H03B5/1228 , G11C7/222 , H03B5/1215 , H03B5/124
摘要： A voltage-controlled oscillator includes an oscillating unit configured to output first and second output clock signals at first and second nodes, respectively, the first and second output clock signals having a frequency that is variable in response to a control voltage. An active element unit connected to the oscillating unit is configured to maintain oscillation of the oscillating unit. A bias current generating unit connected to the active element unit at a bias node provides a bias current to the bias node and is adapted to adjust the bias current in response to a control code. First and second capacitor blocks connected to the oscillating unit and the active element unit provide first and second load capacitances, respectively, to the first and second nodes, respectively, in response to the control code.
摘要翻译：压控振荡器包括：振荡单元，被配置为分别在第一和第二节点处输出第一和第二输出时钟信号，第一和第二输出时钟信号具有响应于控制电压而变化的频率。连接到振荡单元的有源元件单元被配置为保持振荡单元的振荡。在偏置节点处连接到有源元件单元的偏置电流产生单元向偏置节点提供偏置电流，并且适于响应于控制代码调整偏置电流。连接到振荡单元和有源元件单元的第一和第二电容器块分别响应于控制代码分别向第一和第二节点提供第一和第二负载电容。

7. 发明申请

US20110298499A1 INTERNAL VOLTAGE GENERATOR AND INTEGRATED CIRCUIT DEVICE INCLUDING THE SAME 审中-公开
标题翻译：内部电压发生器和集成电路装置，包括它们
公开(公告)号：US20110298499A1
公开(公告)日：2011-12-08
申请号：US13110242
申请日：2011-05-18
申请人： Ho-Seok Seol , Seung-Jun Bae
发明人： Ho-Seok Seol , Seung-Jun Bae
IPC分类号： G05F3/16
CPC分类号： G11C5/147 , G11C11/4074
摘要： An internal voltage generator includes a comparison unit, a driving circuit and a bias unit. The comparison unit compares a reference voltage and an internal voltage and is configured to output a comparison voltage, which is based on a difference between the reference voltage and the internal voltage. The driving circuit receives the comparison voltage and an external power supply voltage and is configured to output the internal voltage to an output node in response to the comparison voltage. The bias unit receives the internal voltage and is configured to adaptively adjust a bias current that flows through the bias unit to drive the comparison unit, in consideration of a level of the internal voltage.
摘要翻译：内部电压发生器包括比较单元，驱动电路和偏置单元。比较单元比较参考电压和内部电压，并且被配置为输出基于参考电压和内部电压之间的差的比较电压。驱动电路接收比较电压和外部电源电压，并且被配置为响应于比较电压将内部电压输出到输出节点。偏置单元接收内部电压，并且被配置为考虑到内部电压的电平，自适应地调节流过偏置单元的偏置电流以驱动比较单元。

8. 发明授权

US10242731B2 Memory device for controlling refresh operation by using cell characteristic flags 有权
公开(公告)号：US10242731B2
公开(公告)日：2019-03-26
申请号：US14956792
申请日：2015-12-02
申请人： Ki-ho Hyun , Kyo-min Sohn , Je-min Ryu , Ho-Seok Seol
发明人： Ki-ho Hyun , Kyo-min Sohn , Je-min Ryu , Ho-Seok Seol
IPC分类号： G11C11/408 , G11C11/406 , G11C11/4093
摘要： A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式