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1. 发明授权

US06946882B2 Current sense amplifier 失效
标题翻译：电流检测放大器
公开(公告)号：US06946882B2
公开(公告)日：2005-09-20
申请号：US10326367
申请日：2002-12-20
申请人： Dietmar Gogl , William Robert Reohr , John Kenneth DeBrosse
发明人： Dietmar Gogl , William Robert Reohr , John Kenneth DeBrosse
IPC分类号： G11C7/06 , G01R19/00
CPC分类号： G11C7/067 , G11C2207/063
摘要： A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the load device may be a hard-wired current mirror, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal and the second input signal.
摘要翻译：具有互补参考单元和可配置负载器件的对称高速电流检测放大器，其消除了架构相关的电容失配贡献。电流检测放大器适用于对称感测架构，并且包括可配置的负载装置。电流检测放大器包括电压比较器，耦合在电压比较器的第一输入端和第一输入信号之间的第一钳位装置，第一钳位装置耦合到参考电压。第二钳位装置耦合在电压比较器的第二输入端和第二输入信号之间，第二钳位装置耦合到参考电压。负载装置可以包括耦合在电压比较器的第一和第二输入端之间的电流镜。电流镜可以通过选择晶体管来配置。或者，负载装置可以是硬连线电流镜，并且可以使用多路复用器来选择第一输入信号还是第二输入信号连接到电流镜的第一或第二侧。可以在适当的节点添加可配置的虚拟负载，以优化容性负载并提高放大器的速度。均衡装置可以耦合在电压比较器的第一和第二输入端之间以及第一输入信号和第二输入信号之间。

2. 发明授权

US06944049B2 Magnetic tunnel junction memory cell architecture 失效
标题翻译：磁隧道结记忆单元架构
公开(公告)号：US06944049B2
公开(公告)日：2005-09-13
申请号：US10422100
申请日：2003-04-24
申请人： Heinz Hoenigschmid , Dietmar Gogl , John Kenneth DeBrosse
发明人： Heinz Hoenigschmid , Dietmar Gogl , John Kenneth DeBrosse
IPC分类号： G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/22 , G11C11/00
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/15 , G11C11/16
摘要： A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.
摘要翻译：存储器件包括具有磁性隧道结结构的磁性隧道结存储器单元和读取开关。在一个示例中，读取开关连接到用于写入磁性隧道结结构的导体。在另一示例中，读开关是通过深通孔接触电耦合到磁隧道结结构的晶体管。在另一示例中，存储器件包括多个磁性隧道结存储器单元和分别与单元相关联的多个导体，用于将信息写入相关联的磁性隧道结结构。每个读取开关连接到与读取开关所在的单元以外的磁性隧道结单元相关联的导体。

3. 发明授权

US06778431B2 Architecture for high-speed magnetic memories 有权
标题翻译：高速磁记忆架构
公开(公告)号：US06778431B2
公开(公告)日：2004-08-17
申请号：US10318709
申请日：2002-12-13
申请人： Dietmar Gogl , William Robert Reohr , Roy Edwin Scheuerlein
发明人： Dietmar Gogl , William Robert Reohr , Roy Edwin Scheuerlein
IPC分类号： G11C700
CPC分类号： G11C11/1693 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.
摘要翻译：磁存储器电路包括多个存储器单元和耦合到存储器单元的多个位线，用于选择性地访问一个或多个存储器单元。存储器电路包括至少一个位线编程电路，可配置为用于产生用于写入至少一个存储器单元的逻辑状态的编程电流的电流源和/或用于返回编程电流的电流吸收器，以及第一组开关。至少在存储器单元的读取操作期间禁用第一组开关，并且在存储器单元的写入操作期间选择性地使能第一组开关的至少一部分。第一组开关中的每个开关被配置为响应于第一控制信号选择性地将至少一个位线编程电路耦合到对应的位线。存储器电路还包括至少一个读出放大器和第二组开关。至少在存储器单元的写入操作期间禁用第二组开关，并且在存储器单元的读取操作期间，第二组开关的至少一部分被选择性地使能。第二组开关中的每个开关被配置为响应于第二控制信号选择性地将至少一个读出放大器耦合到对应的一个位线。

4. 发明申请

US20080310210A1 Semiconductor memory device and method of operation 审中-公开
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20080310210A1
公开(公告)日：2008-12-18
申请号：US11818196
申请日：2007-06-13
申请人： Dietmar Gogl , Ulrich Klostermann
发明人： Dietmar Gogl , Ulrich Klostermann
IPC分类号： G11C7/02
CPC分类号： G11C13/0011 , G11C8/08 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2213/79
摘要： A memory cell is disclosed. The memory cell comprises a storage element including a first terminal and a second terminal, and a select transistor including a first terminal, a second terminal and a control terminal. The voltage at the control terminal of the select transistor affects a current flowing between the first terminal and the second terminal. The first terminal of the select transistor is coupled to the second terminal of the storage element. A bit line is coupled to the first terminal of the storage element, a first word line is coupled to the control terminal of the select transistor, and a second word line is coupled to the second terminal of the select transistor.
摘要翻译：公开了一种存储器单元。存储单元包括存储元件，其包括第一端子和第二端子，以及选择晶体管，其包括第一端子，第二端子和控制端子。选择晶体管的控制端子处的电压影响在第一端子和第二端子之间流动的电流。选择晶体管的第一端子耦合到存储元件的第二端子。位线耦合到存储元件的第一端子，第一字线耦合到选择晶体管的控制端子，第二字线耦合到选择晶体管的第二端子。

5. 发明授权

US07433253B2 Integrated circuit, method of operating an integrated circuit, method of manufacturing an integrated circuit, memory module, stackable memory module 有权
标题翻译：集成电路，集成电路的操作方法，集成电路的制造方法，存储器模块，可堆叠存储器模块
公开(公告)号：US07433253B2
公开(公告)日：2008-10-07
申请号：US11768508
申请日：2007-06-26
申请人： Dietmar Gogl , Hans-Heinrich Viehmann
发明人： Dietmar Gogl , Hans-Heinrich Viehmann
IPC分类号： G11C7/02 , G11C11/00
CPC分类号： G11C7/067 , G11C5/02 , G11C5/04 , G11C11/1673 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/004 , G11C2013/0054 , G11C2207/063 , G11C2213/71 , G11C2213/79
摘要： An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamping device coupled between the second input of the voltage comparator and a second input signal node, a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, and a sensing scheme including an actively balanced capacitance coupled to the source and drain of the second transistor.
摘要翻译：集成电路具有电流检测放大器，其包括具有第一输入，第二输入和输出的电压比较器; 耦合在电压比较器的第一输入端和第一输入信号节点之间的第一钳位装置，耦合在电压比较器的第二输入端和第二输入信号节点之间的第二钳位装置，具有第一侧和第二电流镜第一侧包括耦合在电压源和第一钳位装置之间的第一晶体管和电流镜第二侧，其包括耦合在电压源和第二钳位装置之间的第二晶体管，以及感测方案，包括主动平衡耦合到第二晶体管的源极和漏极的电容。

6. 发明申请

US20070121391A1 Magnetoresistive random access memory array 有权
标题翻译：磁阻随机存取存储器阵列
公开(公告)号：US20070121391A1
公开(公告)日：2007-05-31
申请号：US11288494
申请日：2005-11-29
申请人： Dietmar Gogl , Daniel Braun
发明人： Dietmar Gogl , Daniel Braun
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C8/10
摘要： A magnetic memory is disclosed. In one embodiment, the magnetic memory array includes a plurality of cell columns and a pair of reference cell columns, including a first reference cell column and a second reference cell column. A comparator is provided with a first and a second input terminal. A switching circuit is configured to connect each of the cell columns to the first input terminal and the pair of reference cell columns coupled in parallel to the second input terminal, and configured to connect the first reference cell column to the first input terminal and the second reference cell column to the second input terminal.
摘要翻译：公开了磁存储器。在一个实施例中，磁存储阵列包括多个单元列和一对参考单元列，包括第一参考单元列和第二参考单元列。比较器具有第一和第二输入端。开关电路被配置为将每个单元列连接到与第二输入端并联耦合的第一输入端和一对参考单元列，并且被配置为将第一参考单元列连接到第一输入端，而第二参考单元列参考单元格列到第二个输入端。

7. 发明授权

US07200033B2 MRAM with coil for creating offset field 有权
标题翻译：带有线圈的MRAM用于创建偏移场
公开(公告)号：US07200033B2
公开(公告)日：2007-04-03
申请号：US10998808
申请日：2004-11-30
申请人： Daniel Braun , Dietmar Gogl
发明人： Daniel Braun , Dietmar Gogl
IPC分类号： G11C11/00 , G11C5/06 , G11C11/14 , G11C11/15 , G11C7/02
CPC分类号： H01L27/222 , G11C11/16
摘要： An MRAM memory chip includes a plurality of magnetoresistive memory cells each including a magnetic tunnel junction having first (fixed) and second (free) magnetic regions, where the second magnetic region includes at least two ferromagnetic layers that are antiferromagnetically coupled, wherein a coil surrounds the memory chip for creating a magnetic offset field. Further, a method of writing to an MRAM chip includes bringing the memory cells into an active state exhibiting a reduced switching field before writing thereto and bringing the memory cells into a passive state exhibiting enlarged switching field after writing thereto.
摘要翻译： MRAM存储器芯片包括多个磁阻存储单元，每个磁阻存储单元包括具有第一（固定）和第二（自由）磁区的磁性隧道结，其中第二磁区包括反铁磁耦合的至少两个铁磁层，其中线圈围绕用于产生磁偏移场的存储芯片。此外，写入MRAM芯片的方法包括在写入之前使存储单元进入呈现减小的开关场的有效状态，并且在写入之后使存储单元成为展现放大开关场的被动状态。

8. 发明申请

US20060104136A1 Sense amplifier bitline boost circuit 有权
标题翻译：感应放大器位线升压电路
公开(公告)号：US20060104136A1
公开(公告)日：2006-05-18
申请号：US10988787
申请日：2004-11-15
申请人： Dietmar Gogl , Hans-Heinrich Viehmann
发明人： Dietmar Gogl , Hans-Heinrich Viehmann
IPC分类号： G11C7/02
CPC分类号： G11C5/145 , G11C7/06 , G11C7/12 , G11C11/16 , G11C2207/063
摘要： A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost circuit to shorten the charging time for parasitic circuit capacitance. The bitline boost circuit includes a source follower coupled to a reference voltage and a switch coupled to another voltage source. The switch is enabled to conduct during an initial period of sensing the resistance of the memory cell. The source follower in the bitline boost circuit is configured to clamp the voltage of an input signal at substantially the same level as the clamping devices, and to provide additional current to shorten the period for charging parasitic capacitance. The resulting current sense amplifier can be used to implement a memory device with fast and reliable read times and low manufacturing cost.
摘要翻译：包括钳位装置和电流镜的电流检测放大器被配置为使用位线升压电路感测MTJ存储器单元的电阻，以缩短寄生电路电容的充电时间。位线升压电路包括耦合到参考电压的源极跟随器和耦合到另一个电压源的开关。在感测存储单元的电阻的初始时段期间，该开关能够导通。位线升压电路中的源极跟随器被配置为将输入信号的电压钳位在与钳位装置基本相同的电平上，并提供额外的电流以缩短对寄生电容充电的周期。所得到的电流检测放大器可用于实现具有快速可靠的读取时间和低制造成本的存储器件。

9. 发明授权

US06807089B2 Method for operating an MRAM semiconductor memory configuration 失效
标题翻译：用于操作MRAM半导体存储器配置的方法
公开(公告)号：US06807089B2
公开(公告)日：2004-10-19
申请号：US10685082
申请日：2003-10-14
申请人： Dietmar Gogl , Till Schloesser
发明人： Dietmar Gogl , Till Schloesser
IPC分类号： G11C1100
CPC分类号： G11C11/15
摘要： In a method for operating an MRAM semiconductor memory configuration, for the purpose of reading an item of stored information, reversible magnetic changes are made to the TMR cell and a current that is momentarily altered as a result is compared with the original read signal. As a result, the TMR memory cell itself can serve as a reference, even though the information in the TMR memory cell is not destroyed, i.e. writing-back does not have to be effected. The method can preferably be applied to an MRAM memory configuration in which a plurality of TMR cells are connected, in parallel, to a selection transistor and in which there is a write line which is not electrically connected to the memory cell.
摘要翻译：在用于操作MRAM半导体存储器配置的方法中，为了读取存储的信息的项目，对TMR单元进行可逆的磁性改变，并且将与暂时改变的电流作为结果与原始读取信号进行比较。结果，TMR存储单元本身可以用作参考，即使TMR存储单元中的信息不被破坏，即不需要进行回写。该方法可以优选地应用于其中多个TMR单元并联连接到选择晶体管并且其中存在没有电连接到存储器单元的写入线的MRAM存储器配置。

10. 发明授权

US06483768B2 Current driver configuration for MRAM 有权
标题翻译： MRAM的当前驱动程序配置
公开(公告)号：US06483768B2
公开(公告)日：2002-11-19
申请号：US09898221
申请日：2001-07-03
申请人： Thomas Böhm , Dietmar Gogl , Gerhard Müller , Thomas Röhr
发明人： Thomas Böhm , Dietmar Gogl , Gerhard Müller , Thomas Röhr
IPC分类号： G11C800
CPC分类号： G11C11/16 , G11C7/12
摘要： A current driver configuration for MRAMs includes word-line drivers and bit-line drivers at respective first ends of word lines and bit lines. The word line drivers and the bit line drivers each include a series circuit formed by an n-channel field-effect transistor and a current source. Further series circuits are provided at the respective second ends of the word lines and the bit lines. Each of the further series circuits includes a second n-channel field-effect transistor and a voltage source.
摘要翻译： MRAM的当前驱动器配置包括在字线和位线的相应第一端处的字线驱动器和位线驱动器。字线驱动器和位线驱动器各自包括由n沟道场效应晶体管和电流源形成的串联电路。在字线和位线的各自的第二端设置有更多的串联电路。每个其它串联电路包括第二n沟道场效应晶体管和电压源。

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