专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06778431B2 Architecture for high-speed magnetic memories 有权
标题翻译：高速磁记忆架构
公开(公告)号：US06778431B2
公开(公告)日：2004-08-17
申请号：US10318709
申请日：2002-12-13
申请人： Dietmar Gogl , William Robert Reohr , Roy Edwin Scheuerlein
发明人： Dietmar Gogl , William Robert Reohr , Roy Edwin Scheuerlein
IPC分类号： G11C700
CPC分类号： G11C11/1693 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.
摘要翻译：磁存储器电路包括多个存储器单元和耦合到存储器单元的多个位线，用于选择性地访问一个或多个存储器单元。存储器电路包括至少一个位线编程电路，可配置为用于产生用于写入至少一个存储器单元的逻辑状态的编程电流的电流源和/或用于返回编程电流的电流吸收器，以及第一组开关。至少在存储器单元的读取操作期间禁用第一组开关，并且在存储器单元的写入操作期间选择性地使能第一组开关的至少一部分。第一组开关中的每个开关被配置为响应于第一控制信号选择性地将至少一个位线编程电路耦合到对应的位线。存储器电路还包括至少一个读出放大器和第二组开关。至少在存储器单元的写入操作期间禁用第二组开关，并且在存储器单元的读取操作期间，第二组开关的至少一部分被选择性地使能。第二组开关中的每个开关被配置为响应于第二控制信号选择性地将至少一个读出放大器耦合到对应的一个位线。

2. 发明授权

US06269040B1 Interconnection network for connecting memory cells to sense amplifiers 有权
标题翻译：用于将存储单元连接到读出放大器的互连网络
公开(公告)号：US06269040B1
公开(公告)日：2001-07-31
申请号：US09603632
申请日：2000-06-26
申请人： William Robert Reohr , Roy Edwin Scheuerlein
发明人： William Robert Reohr , Roy Edwin Scheuerlein
IPC分类号： G11C702
CPC分类号： G11C7/1069 , G11C7/06 , G11C7/1051 , G11C7/18
摘要： An interconnection network for connecting memory cells to sense amplifiers in a memory device includes a plurality of sub-arrays having memory cells, a plurality of switch units each of which is associated with a corresponding one of the plurality of sub-arrays, and true and complement input lines of the sense amplifiers each of which receives data from a selected memory cell via an input line and reference from reference cells via the other input line. The reference, which is a mid-level of data in the memory cells, is obtained from a reference cell having the mid-level value. Alternatively, a mid-level reference may be obtained by averaging data of logic values “1” and “0” stored in different reference cells. The reference cells may be disposed in the sub-arrays or outside the sub-arrays. The interconnection network of the present invention has symmetric configuration so that networks of the input lines of the sense amplifiers have substantially equal structure. Both inputs of a sense amplifier have substantially equal number of connections to data columns and reference columns.
摘要翻译：用于将存储器单元连接到存储器件中的感测放大器的互连网络包括具有存储器单元的多个子阵列，多个开关单元，每个开关单元与多个子阵列中的相应一个子阵列相关联，读出放大器的补码输入线，每个读出放大器经由输入线从参考单元经由输入线接收数据，并经由另一输入线从参考单元接收数据。作为存储器单元中的数据中间值的参考是从具有中间值的参考单元获得的。或者，可以通过平均存储在不同参考单元中的逻辑值“1”和“0”的数据来获得中间级参考。参考单元可以设置在子阵列中或子阵列外部。本发明的互连网络具有对称配置，使得感测放大器的输入线的网络具有基本相同的结构。读出放大器的两个输入端具有与数据列和参考列基本上相等数量的连接。

3. 发明授权

US06404671B1 Data-dependent field compensation for writing magnetic random access memories 失效
标题翻译：用于写入磁随机存取存储器的数据相关磁场补偿
公开(公告)号：US06404671B1
公开(公告)日：2002-06-11
申请号：US09933584
申请日：2001-08-21
申请人： William Robert Reohr , Roy Edwin Scheuerlein
发明人： William Robert Reohr , Roy Edwin Scheuerlein
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： A field compensation circuit for selectively writing one or more selected magnetic memory cells in a magnetic random access memory (MRAM) includes a controller for detecting a characteristic representative of an anticipated interaction between a magnetic field emanating from a bit line corresponding to a selected memory cell and at least one stray magnetic field emanating from one or more bit lines associated with one or more memory cells in close relative proximity to the selected memory cell. A control signal generated by the controller is indicative of the detected characteristic. The field compensation circuit further includes a programmable current source operatively coupled to the bit line corresponding to the selected memory cell, the programmable current source including an input for receiving the control signal. The programmable current source generates a write current having a magnitude which varies in response to the control signal. In this manner, the write current flowing through a given bit line corresponding to a selected memory cell can be selectively adjusted to compensate for magnetic field interaction with adjacent bit lines.
摘要翻译：一种用于选择性地将一个或多个所选择的磁存储器单元写入磁随机存取存储器（MRAM）的场补偿电路包括一个控制器，用于检测表示从对应于所选存储单元的位线发出的磁场之间的预期相互作用的特性以及从与所选择的存储器单元相对靠近的一个或多个存储器单元相关联的一个或多个位线发出的至少一个杂散磁场。由控制器产生的控制信号表示检测到的特性。场补偿电路还包括可操作地耦合到对应于所选存储单元的位线的可编程电流源，可编程电流源包括用于接收控制信号的输入端。可编程电流源产生具有响应于控制信号而变化的幅度的写入电流。以这种方式，可以选择性地调节流过与所选存储单元相对应的给定位线的写入电流，以补偿与相邻位线的磁场相互作用。

4. 发明授权

US06975555B2 Magnetic random access memory using memory cells with rotated magnetic storage elements 有权
公开(公告)号：US06975555B2
公开(公告)日：2005-12-13
申请号：US10976598
申请日：2004-10-29
申请人： Yu Lu , William Robert Reohr , Roy Edwin Scheuerlein
发明人： Yu Lu , William Robert Reohr , Roy Edwin Scheuerlein
IPC分类号： G11C7/00 , G11C11/15 , G11C11/16
CPC分类号： G11C11/16
摘要： A magnetic random access memory circuit comprises a plurality of magnetic memory cells, each of the memory cells including a magnetic storage element having an easy axis and a hard axis associated therewith, and a plurality of column lines and row lines for selectively accessing one or more of the memory cells, each of the memory cells being proximate to an intersection of one of the column lines and one of the row lines. Each of the magnetic memory cells is arranged such that the easy axis is substantially parallel to a direction of flow of a sense current and the hard axis is substantially parallel to a direction of flow of a write current.

5. 发明授权

US06335890B1 Segmented write line architecture for writing magnetic random access memories 有权
标题翻译：用于写入磁随机存取存储器的分段写行架构
公开(公告)号：US06335890B1
公开(公告)日：2002-01-01
申请号：US09703963
申请日：2000-11-01
申请人： William Robert Reohr , Roy Edwin Scheuerlein
发明人： William Robert Reohr , Roy Edwin Scheuerlein
IPC分类号： G11C1102
CPC分类号： G11C11/14 , G11C11/16
摘要： An architecture for selectively writing one or more magnetic memory cells in a magnetic random access memory (MRAM) device comprises at least one write line including a global write line conductor and a plurality of segmented write line conductors connected thereto, the global write line conductor being substantially isolated from the memory cells. The architecture further includes a plurality of segmented groups, each segmented group including a plurality of memory cells operatively coupled to a corresponding segmented write line conductor, and a plurality of segmented group select switches, each group select switch being operatively connected between a corresponding segmented write line conductor and a write line current return conductor, the group select switch including a group select input for receiving a group select signal, the group select switch substantially completing an electrical circuit between the corresponding segmented write line conductor and the write line current return conductor in response to the group select signal. A plurality of bit lines are operatively coupled to the magnetic memory cells for selectively writing the state of the memory cells.
摘要翻译：一种用于在磁随机存取存储器（MRAM）装置中选择性地写入一个或多个磁存储单元的架构包括至少一条写入线，包括全局写线导体和连接到其上的多个分段写线导体，全局写线导体为基本上与记忆细胞分离。该架构还包括多个分段组，每个分段组包括可操作地耦合到对应的分段写线路导体的多个存储单元，以及多个分组组选择开关，每个组选择开关可操作地连接在相应的分段写入线路导体和写入线路电流返回导体，组选择开关包括用于接收组选择信号的组选择输入，组选择开关基本上完成对应的分段写入线导体和写入线电流返回导体之间的电路响应组选择信号。多个位线可操作地耦合到磁存储器单元，用于选择性地写入存储单元的状态。

6. 发明授权

US06816431B1 Magnetic random access memory using memory cells with rotated magnetic storage elements 有权
标题翻译：使用具有旋转磁存储元件的存储单元的磁性随机存取存储器
公开(公告)号：US06816431B1
公开(公告)日：2004-11-09
申请号：US10446297
申请日：2003-05-28
申请人： Yu Lu , William Robert Reohr , Roy Edwin Scheuerlein
发明人： Yu Lu , William Robert Reohr , Roy Edwin Scheuerlein
IPC分类号： G11C1115
CPC分类号： G11C11/16
摘要： A magnetic random access memory circuit comprises a plurality of magnetic memory cells, each of the memory cells including a magnetic storage element having an easy axis and a hard axis associated therewith, and a plurality of column lines and row lines for selectively accessing one or more of the memory cells, each of the memory cells being proximate to an intersection of one of the column lines and one of the row lines. Each of the magnetic memory cells is arranged such that the easy axis is substantially parallel to a direction of flow of a sense current and the hard axis is substantially parallel to a direction of flow of a write current.
摘要翻译：磁性随机存取存储器电路包括多个磁存储器单元，每个存储单元包括具有容易轴的磁存储元件和与其相关联的硬轴，以及多个列线和行线，用于选择性地访问一个或多个的存储单元，每个存储器单元靠近一列列线和一行行的交点。每个磁存储单元被布置成使得容易轴基本上平行于感测电流的流动方向，并且硬轴基本上平行于写入电流的流动方向。

7. 发明授权

US06191989B1 Current sensing amplifier 有权
标题翻译：电流检测放大器
公开(公告)号：US06191989B1
公开(公告)日：2001-02-20
申请号：US09520668
申请日：2000-03-07
申请人： Wing Kin Luk , William Robert Reohr , Roy Edwin Scheuerlein
发明人： Wing Kin Luk , William Robert Reohr , Roy Edwin Scheuerlein
IPC分类号： G11C1122
CPC分类号： G11C11/15 , G11C7/062 , G11C7/067 , G11C2207/063
摘要： A current sensing amplifier for detecting a small current difference between a pair of variable resistance loads comprises a first amplifier and a second amplifier. The first amplifier comprises a voltage clamp including first and second outputs, the voltage clamp being coupled to the pair of variable resistance loads and substantially fixing a predetermined voltage across the variable resistance loads, the voltage clamp transferring the measured current difference to the first and second outputs. The first amplifier further includes a differential current source coupled to the first and second outputs. The second amplifier includes first and second inputs and an output, the first and second inputs being coupled to the first and second outputs, respectively, of the first amplifier. The current sensing amplifier detects small positive and/or negative differences in current developed between two variable resistance loads and converts the current difference into an output signal commensurate with standard CMOS logic levels. Sensing speeds are improved further by equalizing predetermined internal nodes of the sensing amplifier prior to sensing a new signal.
摘要翻译：用于检测一对可变电阻负载之间的小电流差的电流感测放大器包括第一放大器和第二放大器。该第一放大器包括一个包括第一和第二输出的电压钳，该电压钳与一对可变电阻负载耦合，并且基本上固定一可变电阻负载上的预定电压，该电压钳将测得的电流差转移到第一和第二输出。第一放大器还包括耦合到第一和第二输出的差分电流源。第二放大器包括第一和第二输入和输出，第一和第二输入分别耦合到第一放大器的第一和第二输出。电流感测放大器检测在两个可变电阻负载之间产生的电流的小的正和负差异，并将电流差转换成与标准CMOS逻辑电平相当的输出信号。通过在感测新信号之前平衡感测放大器的预定内部节点，进一步提高感测速度。

8. 发明授权

US06562634B2 Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method of forming the same 有权
标题翻译：连接到磁性隧道结并与金属导体自对准的二极管及其形成方法
公开(公告)号：US06562634B2
公开(公告)日：2003-05-13
申请号：US09811759
申请日：2001-03-20
申请人： Gary Bela Bronner , Stephen McConnell Gates , Roy Edwin Scheuerlein
发明人： Gary Bela Bronner , Stephen McConnell Gates , Roy Edwin Scheuerlein
IPC分类号： H01L2100
CPC分类号： H01L27/224 , B82Y10/00
摘要： A magneto-resistive memory cell and a method of forming the memory cell, includes a substrate, a single crystalline semiconductor diode formed in the substrate; and a first thin film conductor recessed in the substrate, and a second thin film conductor formed above a magnetic tunnel junction formed on the diode. The diode and the first thin film conductor share a non-planar common surface, such that the metal tunnel junction is a predetermined distance from the thin film conductor.
摘要翻译：磁阻存储器单元和形成存储单元的方法包括：衬底，形成在衬底中的单晶半导体二极管; 以及在基板上凹陷的第一薄膜导体，以及形成在二极管上形成的磁性隧道结上方的第二薄膜导体。二极管和第一薄膜导体共用非平面公共表面，使得金属隧道结距离薄膜导体预定的距离。

9. 发明授权

US06515897B1 Magnetic random access memory using a non-linear memory element select mechanism 有权
标题翻译：磁性随机存取存储器采用非线性存储元件选择机制
公开(公告)号：US06515897B1
公开(公告)日：2003-02-04
申请号：US09549211
申请日：2000-04-13
申请人： Douwe Johannes Monsma , Stuart Stephen Papworth Parkin , Roy Edwin Scheuerlein
发明人： Douwe Johannes Monsma , Stuart Stephen Papworth Parkin , Roy Edwin Scheuerlein
IPC分类号： G11C1115
CPC分类号： G11C11/15
摘要： A non-volatile memory array having a substrate, a first plurality of electrically conductive traces formed on the substrate, a second plurality of electrically conductive traces formed on the substrate and overlapping first plurality of traces at a plurality of intersection regions, and a plurality of memory cells. Each memory cell is located at an intersection region between one of the first plurality of traces and one of the second plurality of traces. At least one memory cell includes a non-linear magnetic tunnel junction storage element. The non-linear magnetic tunnel junction storage element has at least a first ferromagnetic layer, a barrier layer and a second ferromagnetic layer. The non-linear magnetic tunnel junction storage element has a non-linearity that is defined by a current having a first magnitude flowing through the non-linear magnetic tunnel junction storage element for a bias across the non-linear magnetic tunnel junction storage element of about 0.5 VA that is ten times or more smaller than a current having a second magnitude flowing through the non-linear magnetic tunnel junction storage element for a bias across the non-linear magnetic tunnel junction storage element of about 1 VA, where VA is an operating voltage for a memory cell. The non-linearity is used for minimizing sneak currents through unselected cells, and allowing read or write selection of a particular memory element in a large array.
摘要翻译：一种非易失性存储器阵列，其具有衬底，形成在衬底上的第一多个导电迹线，形成在衬底上的第二多个导电迹线，并且在多个交叉区域上与第一多个迹线重叠，记忆细胞每个存储器单元位于第一多个迹线之一和第二多个迹线中的一个之间的交叉区域。至少一个存储单元包括非线性磁性隧道结存储元件。非线性磁性隧道结存储元件具有至少第一铁磁层，阻挡层和第二铁磁层。非线性磁性隧道结存储元件具有非线性，其由具有流过非线性磁性隧道结存储元件的第一幅度的电流限定，用于横跨非线性磁性隧道结存储元件的偏置约为 0.5VA是比具有第二幅度的电流的十倍或更小，该电流流过非线性磁性隧道结存储元件，用于跨过非线性磁性隧道结存储元件的约1VA的偏压，其中VA是操作的一个存储单元的电压。非线性用于通过未选择的单元最小化潜行电流，并允许以大阵列对特定存储器元件进行读取或写入选择。

10. 发明授权

US06331944B1 Magnetic random access memory using a series tunnel element select mechanism 有权
标题翻译：磁性随机存取存储器采用串联隧道元素选择机制
公开(公告)号：US06331944B1
公开(公告)日：2001-12-18
申请号：US09549172
申请日：2000-04-13
申请人： Douwe Johannes Monsma , Stuart Stephen Papworth Parkin , Roy Edwin Scheuerlein
发明人： Douwe Johannes Monsma , Stuart Stephen Papworth Parkin , Roy Edwin Scheuerlein
IPC分类号： G11C1300
CPC分类号： H01L27/224 , G11C11/15
摘要： A non-volatile memory array includes first and second pluralities of electrically conductive traces formed on a substrate. The second plurality of electrically conductive traces overlap first plurality of traces at a plurality of intersection regions. Each of a plurality of memory cells is located at an intersection region between one of the first plurality of traces and one of the second plurality of traces. At least one of the memory cells includes a non-linear selection element in series with a magnetic tunnel junction storage element. The non-linear selection element includes at least a first metallic electrode layer, a barrier layer and a second metallic electrode layer metal. The non-linear selection element has a non-linearity defined by a current having a first magnitude flowing through the non-linear selection element for a first bias voltage across the non-linear selection element that is ten times or more smaller than a current having a second magnitude flowing through the non-linear selection element for a second bias voltage across the non-linear selection element, such that the second bias voltage is about two times greater than the first bias voltage. The magnetic tunnel junction storage element includes at least a first ferromagnetic layer, a thin insulating layer and a second ferromagnetic layer.
摘要翻译：非易失性存储器阵列包括形成在衬底上的第一和第二多个导电迹线。第二多个导电迹线在多个交叉区域处与第一多个迹线重叠。多个存储器单元中的每一个位于第一多个迹线中的一个和第二多个迹线中的一个之间的交叉区域。至少一个存储单元包括与磁性隧道结存储元件串联的非线性选择元件。非线性选择元件至少包括第一金属电极层，阻挡层和第二金属电极层金属。非线性选择元件具有由具有流过非线性选择元件的第一幅度的电流定义的非线性，该电流是非线性选择元件的跨越非线性选择元件的第一偏置电压的十倍或更小，第二幅度流经所述非线性选择元件，以跨越所述非线性选择元件的第二偏置电压流动，使得所述第二偏置电压大约是所述第一偏置电压的两倍。磁性隧道结存储元件至少包括第一铁磁层，薄绝缘层和第二铁磁层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式