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1. 发明授权

US07254073B2 Memory device having an array of resistive memory cells 有权
标题翻译：具有电阻存储单元阵列的存储器件
公开(公告)号：US07254073B2
公开(公告)日：2007-08-07
申请号：US11238116
申请日：2005-09-29
申请人： Thomas Röhr
发明人： Thomas Röhr
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C13/0011 , G11C13/004 , G11C2013/0054 , G11C2213/79
摘要： A memory device including an array of resistive memory cells, which are arranged in columns and rows, and wherein each resistive memory cell each is connected to a word line, to a bit line, and to a reference electrode. The word lines are assigned to the rows and the bit lines are assigned to the columns. The resistive state of the resistive memory cells corresponds to a logical state thereof, and the memory device further comprises an evaluation device, which is coupled to the bit lines, for evaluating the resistive state of at least one of the resistive memory cells during a reading operation. The respective resistive memory cell is selected by addressing the word line to which the resistive memory cell is connected.
摘要翻译：一种存储器件，包括排列成列和行的电阻存储器单元阵列，并且其中每个电阻性存储单元各自连接到字线，位线和参考电极。字线被分配给行，位线被分配给列。电阻存储器单元的电阻状态对应于其逻辑状态，并且存储器件还包括耦合到位线的评估器件，用于在读取期间评估至少一个电阻存储器单元的电阻状态操作。相应的电阻性存储单元是通过寻址与电阻式存储单元连接的字线来选择的。

2. 发明授权

US06483768B2 Current driver configuration for MRAM 有权
标题翻译： MRAM的当前驱动程序配置
公开(公告)号：US06483768B2
公开(公告)日：2002-11-19
申请号：US09898221
申请日：2001-07-03
申请人： Thomas Böhm , Dietmar Gogl , Gerhard Müller , Thomas Röhr
发明人： Thomas Böhm , Dietmar Gogl , Gerhard Müller , Thomas Röhr
IPC分类号： G11C800
CPC分类号： G11C11/16 , G11C7/12
摘要： A current driver configuration for MRAMs includes word-line drivers and bit-line drivers at respective first ends of word lines and bit lines. The word line drivers and the bit line drivers each include a series circuit formed by an n-channel field-effect transistor and a current source. Further series circuits are provided at the respective second ends of the word lines and the bit lines. Each of the further series circuits includes a second n-channel field-effect transistor and a voltage source.
摘要翻译： MRAM的当前驱动器配置包括在字线和位线的相应第一端处的字线驱动器和位线驱动器。字线驱动器和位线驱动器各自包括由n沟道场效应晶体管和电流源形成的串联电路。在字线和位线的各自的第二端设置有更多的串联电路。每个其它串联电路包括第二n沟道场效应晶体管和电压源。

3. 发明授权

US06468896B2 Method of fabricating semiconductor components 有权
标题翻译：制造半导体元件的方法
公开(公告)号：US06468896B2
公开(公告)日：2002-10-22
申请号：US09751961
申请日：2000-12-29
申请人： Thomas Röhr , Christine Dehm , Carlos Mazure-Espejo
发明人： Thomas Röhr , Christine Dehm , Carlos Mazure-Espejo
IPC分类号： H01L214763
CPC分类号： H01L28/60 , H01L21/32139 , H01L2924/0002 , Y10S438/95 , H01L2924/00
摘要： Disclosed is a method for producing semiconductor elements including a metal layer (10) configured on a semiconductor substrate (5). The inventive method consists of the following steps: a silicon layer (15) is deposited on a metal layer (10); an etch mask is applied in order to structure the silicon layer (1%); the silicon layer is selectively etched (15) using the etch mask (25); and the metal layer (10) is structured in an etching process using a selectively etched silicon layer (15) as a hard mask.
摘要翻译：公开了一种制造半导体元件的方法，该半导体元件包括配置在半导体衬底（5）上的金属层（10）。本发明的方法包括以下步骤：在金属层（10）上沉积硅层（15）; 为了构造硅层（1％），施加蚀刻掩模; 使用蚀刻掩模（25）选择性地蚀刻硅层（15）; 并且金属层（10）以使用选择性蚀刻的硅层（15）作为硬掩模的蚀刻工艺构成。

4. 发明授权

US06445607B2 Method for operating an integrated memory 失效
标题翻译：操作集成存储器的方法
公开(公告)号：US06445607B2
公开(公告)日：2002-09-03
申请号：US09829288
申请日：2001-04-09
申请人： Robert Esterl , Heinz Hönigschmid , Helmut Kandolf , Thomas Röhr
发明人： Robert Esterl , Heinz Hönigschmid , Helmut Kandolf , Thomas Röhr
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A description is given of a method for operating an integrated memory which has memory cells each having a selection transistor and a storage capacitor with a ferroelectric storage effect. The memory contains a plate line, which is connected to one of the column lines via a series circuit containing a selection transistor and a storage capacitor of respective memory cells. A memory access is carried out according to the “pulsed plate concept”. In this case, the temporal sequence is controlled in such a way that, in an access cycle, the storage capacitor of the memory cell to be selected is in each case charged and discharged by the same amount. An attenuation or destruction of the information stored in the memory cells, which is caused by source-drain leakage currents of unactivated selection transistors, is thus avoided.
摘要翻译：给出了一种用于操作具有存储单元的集成存储器的方法，每个存储单元都具有选择晶体管和具有铁电存储效应的存储电容器。存储器包含板线，其经由包含各个存储器单元的选择晶体管和存储电容器的串联电路连接到列线之一。根据“脉冲板概念”进行记忆存取。在这种情况下，以这样的方式控制时间序列，使得在访问周期中，要选择的存储单元的存储电容器在每种情况下都以相同的量被放电。因此避免了由未激活的选择晶体管的源漏泄漏电流引起的存储在存储单元中的信息的衰减或破坏。

5. 发明授权

US06826075B2 Random access semiconductor memory with reduced signal overcoupling 失效
标题翻译：随机存取半导体存储器，减少信号超耦合
公开(公告)号：US06826075B2
公开(公告)日：2004-11-30
申请号：US09905853
申请日：2001-07-13
申请人： Dietmar Gogl , Thomas Röhr , Heinz Hönigschmid
发明人： Dietmar Gogl , Thomas Röhr , Heinz Hönigschmid
IPC分类号： G11C506
CPC分类号： G11C11/16 , G11C7/18 , H01L27/222
摘要： A memory matrix has at least one cell array including column lines and row lines. Memory elements are situated at points where the row lines and column lines intersect one another. In each case two adjacent lines are guided such that they cross one another in such a way that the two lines change their spatial configurations in sections along the direction in which they run. Thus an overcoupling of signals between the lines is minimized.
摘要翻译：存储器矩阵具有至少一个包括列线和行线的单元阵列。存储元件位于行线和列线彼此相交的点处。在每种情况下，两个相邻的线被引导使得它们彼此交叉，使得两条线沿着它们运行的方向在其部分中改变它们的空间构造。因此，线路之间的信号过度耦合被最小化。

6. 发明授权

US06645809B2 Process for producing a capacitor configuration 有权
公开(公告)号：US06645809B2
公开(公告)日：2003-11-11
申请号：US09995209
申请日：2001-11-27
申请人： Heinz Hönigschmid , Thomas Röhr
发明人： Heinz Hönigschmid , Thomas Röhr
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/101 , H01L27/11507
摘要： In order to provide a particularly space-saving capacitor configuration in a memory device, a plurality of second electrode regions which are not in direct electrical contact with one another are formed on areas of a first electrode region covered by a dielectric material. During operation of the capacitor configuration, portions of the first electrode region form bottom electrodes which are connected by a connecting region, so that an additional connecting device for the bottom electrodes is not necessary.

7. 发明授权

US06392918B2 Circuit configuration for generating a reference voltage for reading a ferroelectric memory 有权
标题翻译：用于产生用于读取铁电存储器的参考电压的电路配置
公开(公告)号：US06392918B2
公开(公告)日：2002-05-21
申请号：US09817578
申请日：2001-03-26
申请人： Georg Braun , Heinz Hönigschmid , Kurt Hoffmann , Oskar Kowarik , Thomas Röhr
发明人： Georg Braun , Heinz Hönigschmid , Kurt Hoffmann , Oskar Kowarik , Thomas Röhr
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with a constant plate voltage from storage cells of a ferroelectric memory via bit lines. In the circuit, a reference voltage device is formed of two reference cells that are subjected to the action of complementary signals. The reference cells can be simultaneously read out in order to generate the reference voltage in a selection and evaluation device.
摘要翻译：用于产生用于读出的参考电压的电路和用于经由位线从铁电存储器的存储单元以恒定板电压读出的读取输出信号的评估。在该电路中，参考电压装置由经受互补信号的作用的两个参考单元形成。可以同时读出参考单元，以便在选择和评估装置中产生参考电压。

8. 发明授权

US06392445B2 Decoder element for producing an output signal having three different potentials 失效
标题翻译：用于产生具有三个不同电位的输出信号的解码器元件
公开(公告)号：US06392445B2
公开(公告)日：2002-05-21
申请号：US09822027
申请日：2001-03-29
申请人： Thomas Röhr , Heinz Hönigschmid , Zoltan Manyoki , Thomas Böhm , Georg Braun , Ernst Neuhold
发明人： Thomas Röhr , Heinz Hönigschmid , Zoltan Manyoki , Thomas Böhm , Georg Braun , Ernst Neuhold
IPC分类号： G11C800
CPC分类号： H03M5/16
摘要： The decoder element is used for producing an output signal having three different potentials at an output. The second potential is situated between the first potential and the third potential. The decoder element makes it possible to produce any one of the three potentials at its output based upon the potentials on its connections.
摘要翻译：解码器元件用于在输出端产生具有三个不同电位的输出信号。第二电势位于第一电位和第三电位之间。解码器元件使得可以基于其连接上的电位在其输出端产生三个电位中的任何一个。

9. 发明授权

US06259641B1 Integrated memory having sense amplifiers disposed on opposite sides of a cell array 失效
标题翻译：具有设置在单元阵列的相对侧上的读出放大器的集成存储器
公开(公告)号：US06259641B1
公开(公告)日：2001-07-10
申请号：US09560545
申请日：2000-04-28
申请人： Zoltan Manyoki , Thomas Röhr , Thomas Böhm
发明人： Zoltan Manyoki , Thomas Röhr , Thomas Böhm
IPC分类号： G11C700
CPC分类号： G11C11/22 , G11C7/06 , G11C7/1042
摘要： An integrated memory includes a cell array having memory cells disposed at points of intersection of first bit lines and second bit lines with word lines in the cell array. When one of the memory cells is addressed, the memory content is not affected if respective bit lines associated with each of the memory cells are at a standby potential. Sense amplifiers for amplifying data read from the memory cells onto the bit lines are included, each associated with respective first and second bit lines and disposed on opposite sides of the cell array. Also provided are first switching elements, through which each bit line is connected to the associated sense amplifier, and second switching elements, through which each bit line is connected, on that side of its first switching element which is remote from the associated sense amplifier, to a standby potential. Column selection lines are each connected to the control connections of the first and second switching elements in at least one of the first and one of the second bit lines. Each bit line is connected to the standby potential through third switching elements. A first control line is connected to all the third switching elements in the first bit lines, and a second control line is connected to all the third switching elements in the second bit lines.
摘要翻译：集成存储器包括具有存储单元阵列的单元阵列，该存储单元设置在第一位线和第二位线的交点处与单元阵列中的字线。当存储器单元之一被寻址时，如果与每个存储器单元相关联的各个位线处于待机电位，则存储器内容不受影响。包括用于将从存储器单元读取的数据放大到位线的读出放大器，每个与相应的第一和第二位线相关联并且设置在单元阵列的相对侧上。还提供了第一开关元件，每个位线通过该开关元件连接到相关联的读出放大器，以及在其第一开关元件的远离相关读出放大器的该侧上连接每个位线的第二开关元件，到备用电位。列选择线各自连接到第一和第二位线中的至少一个中的第一和第二开关元件的控制连接。每个位线通过第三个开关元件连接到待机电位。第一控制线连接到第一位线中的所有第三开关元件，第二控制线连接到第二位线中的所有第三开关元件。

10. 发明授权

US06255855B1 Integrated circuit having a decoder 有权
标题翻译：具有解码器的集成电路
公开(公告)号：US06255855B1
公开(公告)日：2001-07-03
申请号：US09470310
申请日：1999-12-22
申请人： Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Thomas Röhr , Thomas Böhm
发明人： Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Thomas Röhr , Thomas Böhm
IPC分类号： H03K19084
CPC分类号： G11C8/00 , G11C8/10 , H03K19/084 , H03K19/094 , H03K19/23 , H03M5/16
摘要： An integrated circuit includes a decoder having an output terminal and five input terminals. The decoder has three operating states including a first operating state for generating a first potential at the output terminal, a second operating state for generating a second potential at the output terminal, and a third operating state for generating a third potential at the output terminal. The second potential lies between the first potential and the third potential.
摘要翻译：集成电路包括具有输出端和五个输入端的解码器。解码器具有三个操作状态，包括用于在输出端产生第一电位的第一操作状态，用于在输出端产生第二电位的第二操作状态和用于在输出端产生第三电位的第三操作状态。第二个潜力位于第一个潜力和第三个潜力之间。

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