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1. 发明授权

US07433253B2 Integrated circuit, method of operating an integrated circuit, method of manufacturing an integrated circuit, memory module, stackable memory module 有权
标题翻译：集成电路，集成电路的操作方法，集成电路的制造方法，存储器模块，可堆叠存储器模块
公开(公告)号：US07433253B2
公开(公告)日：2008-10-07
申请号：US11768508
申请日：2007-06-26
申请人： Dietmar Gogl , Hans-Heinrich Viehmann
发明人： Dietmar Gogl , Hans-Heinrich Viehmann
IPC分类号： G11C7/02 , G11C11/00
CPC分类号： G11C7/067 , G11C5/02 , G11C5/04 , G11C11/1673 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/004 , G11C2013/0054 , G11C2207/063 , G11C2213/71 , G11C2213/79
摘要： An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamping device coupled between the second input of the voltage comparator and a second input signal node, a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, and a sensing scheme including an actively balanced capacitance coupled to the source and drain of the second transistor.
摘要翻译：集成电路具有电流检测放大器，其包括具有第一输入，第二输入和输出的电压比较器; 耦合在电压比较器的第一输入端和第一输入信号节点之间的第一钳位装置，耦合在电压比较器的第二输入端和第二输入信号节点之间的第二钳位装置，具有第一侧和第二电流镜第一侧包括耦合在电压源和第一钳位装置之间的第一晶体管和电流镜第二侧，其包括耦合在电压源和第二钳位装置之间的第二晶体管，以及感测方案，包括主动平衡耦合到第二晶体管的源极和漏极的电容。

2. 发明申请

US20060104136A1 Sense amplifier bitline boost circuit 有权
标题翻译：感应放大器位线升压电路
公开(公告)号：US20060104136A1
公开(公告)日：2006-05-18
申请号：US10988787
申请日：2004-11-15
申请人： Dietmar Gogl , Hans-Heinrich Viehmann
发明人： Dietmar Gogl , Hans-Heinrich Viehmann
IPC分类号： G11C7/02
CPC分类号： G11C5/145 , G11C7/06 , G11C7/12 , G11C11/16 , G11C2207/063
摘要： A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost circuit to shorten the charging time for parasitic circuit capacitance. The bitline boost circuit includes a source follower coupled to a reference voltage and a switch coupled to another voltage source. The switch is enabled to conduct during an initial period of sensing the resistance of the memory cell. The source follower in the bitline boost circuit is configured to clamp the voltage of an input signal at substantially the same level as the clamping devices, and to provide additional current to shorten the period for charging parasitic capacitance. The resulting current sense amplifier can be used to implement a memory device with fast and reliable read times and low manufacturing cost.
摘要翻译：包括钳位装置和电流镜的电流检测放大器被配置为使用位线升压电路感测MTJ存储器单元的电阻，以缩短寄生电路电容的充电时间。位线升压电路包括耦合到参考电压的源极跟随器和耦合到另一个电压源的开关。在感测存储单元的电阻的初始时段期间，该开关能够导通。位线升压电路中的源极跟随器被配置为将输入信号的电压钳位在与钳位装置基本相同的电平上，并提供额外的电流以缩短对寄生电容充电的周期。所得到的电流检测放大器可用于实现具有快速可靠的读取时间和低制造成本的存储器件。

3. 发明授权

US06847568B2 Sense amplifier configuration for a semiconductor memory device 失效
标题翻译：用于半导体存储器件的感测放大器配置
公开(公告)号：US06847568B2
公开(公告)日：2005-01-25
申请号：US10662634
申请日：2003-09-15
申请人： Dietmar Gogl , Hans-Heinrich Viehmann
发明人： Dietmar Gogl , Hans-Heinrich Viehmann
IPC分类号： G11C11/15 , G11C7/06 , G11C7/00
CPC分类号： G11C7/067 , G11C7/062 , G11C2207/063
摘要： A memory sense amplifier for a semiconductor memory device is provided with a compensation current source device that generates a compensation current and feeds it to an interconnected bit line. The compensation current is selected in such a manner that during readout a potential gradient can be generated and/or maintained in cooperation with a compensation voltage source device on the selected and interlinked bit line device that is substantially constant over time.
摘要翻译：用于半导体存储器件的存储读出放大器设置有产生补偿电流并将其馈送到互连位线的补偿电流源器件。以这样的方式选择补偿电流，即在读出期间，可以与所选择的和互连的位线装置上的补偿电压源装置协同生成和/或维持电位梯度，所述补偿电压源装置随时间基本上是恒定的。

4. 发明申请

US20080002481A1 Integrated Circuit, Method of Operating an Integrated Circuit, Method of Manufacturing an Integrated Circuit, Memory Module, Stackable Memory Module 有权
标题翻译：集成电路，操作集成电路的方法，制造集成电路的方法，存储器模块，可堆叠存储器模块
公开(公告)号：US20080002481A1
公开(公告)日：2008-01-03
申请号：US11768508
申请日：2007-06-26
申请人： Dietmar Gogl , Hans-Heinrich Viehmann
发明人： Dietmar Gogl , Hans-Heinrich Viehmann
IPC分类号： G11C7/10 , G01R19/00
CPC分类号： G11C7/067 , G11C5/02 , G11C5/04 , G11C11/1673 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/004 , G11C2013/0054 , G11C2207/063 , G11C2213/71 , G11C2213/79
摘要： An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamping device coupled between the second input of the voltage comparator and a second input signal node, a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, and a sensing scheme including an actively balanced capacitance coupled to the source and drain of the second transistor.
摘要翻译：集成电路具有电流检测放大器，其包括具有第一输入，第二输入和输出的电压比较器; 耦合在电压比较器的第一输入端和第一输入信号节点之间的第一钳位装置，耦合在电压比较器的第二输入端和第二输入信号节点之间的第二钳位装置，具有第一侧和第二电流镜第一侧包括耦合在电压源和第一钳位装置之间的第一晶体管和电流镜第二侧，其包括耦合在电压源和第二钳位装置之间的第二晶体管，以及感测方案，包括主动平衡耦合到第二晶体管的源极和漏极的电容。

5. 发明授权

US07251178B2 Current sense amplifier 有权
标题翻译：电流检测放大器
公开(公告)号：US07251178B2
公开(公告)日：2007-07-31
申请号：US10937155
申请日：2004-09-07
申请人： Dietmar Gogl , Hans-Heinrich Viehmann
发明人： Dietmar Gogl , Hans-Heinrich Viehmann
IPC分类号： G11C7/02 , G11C11/00
CPC分类号： G11C7/04 , G11C7/02 , G11C7/062 , G11C7/067 , G11C11/16 , G11C2207/063
摘要： A high-speed current sense amplifier has complementary reference cells and load devices that eliminate capacitive mismatch contributions. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal node. The first clamping device is coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal node. The second clamping device is also coupled to the reference voltage. A current mirror is coupled between the first and second input of the voltage comparator and is coupled to an active capacitance balancing circuit. The active capacitance balancing circuit may be combined with the voltage comparator. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal node and the second input signal node.
摘要翻译：高速电流检测放大器具有补充参考电池和负载器件，可消除电容失配的贡献。电流感测放大器包括电压比较器，耦合在电压比较器的第一输入端和第一输入信号节点之间的第一钳位装置。第一钳位装置耦合到参考电压。第二钳位装置耦合在电压比较器的第二输入端和第二输入信号节点之间。第二钳位装置也耦合到参考电压。电流镜耦合在电压比较器的第一和第二输入端之间并耦合到有源电容平衡电路。有源电容平衡电路可以与电压比较器组合。均衡器件可以耦合在电压比较器的第一和第二输入之间，以及第一输入信号节点和第二输入信号节点之间。

6. 发明申请

US20060239056A1 Generation of MRAM programming currents using external capacitors 审中-公开
标题翻译：使用外部电容器生成MRAM编程电流
公开(公告)号：US20060239056A1
公开(公告)日：2006-10-26
申请号：US11112851
申请日：2005-04-22
申请人： Dietmar Gogl , Hans-Heinrich Viehmann , Daniel Braun
发明人： Dietmar Gogl , Hans-Heinrich Viehmann , Daniel Braun
IPC分类号： G11C5/00
CPC分类号： G11C11/15
摘要： An apparatus comprising a magnetoresistive random access memory (MRAM) and a method of forming the same. The apparatus includes a memory circuit comprising an MRAM cell, and a charge pump circuit electrically coupled to the memory circuit wherein the memory circuit and at least a first portion of the charge pump circuit are fabricated on a single semiconductor chip. The charge pump circuit further includes a second portion comprising at least one capacitor external to the semiconductor chip. The second portion of the charge pump circuit may be packaged in a chip package or external to the chip package.
摘要翻译：一种包括磁阻随机存取存储器（MRAM）的装置及其形成方法。该装置包括存储电路，该存储电路包括MRAM单元和电耦合到存储电路的电荷泵电路，其中存储电路和电荷泵电路的至少第一部分制造在单个半导体芯片上。电荷泵电路还包括在半导体芯片外部包括至少一个电容器的第二部分。电荷泵电路的第二部分可以封装在芯片封装中或芯片封装的外部。

7. 发明申请

US20080080232A1 Active write current adjustment for magneto-resistive random access memory 审中-公开
标题翻译：用于磁阻随机存取存储器的有效写入电流调整
公开(公告)号：US20080080232A1
公开(公告)日：2008-04-03
申请号：US11529569
申请日：2006-09-28
申请人： Andre Sturm , Hans-Heinrich Viehmann , Dietmar Gogl
发明人： Andre Sturm , Hans-Heinrich Viehmann , Dietmar Gogl
IPC分类号： G11C11/00 , G11C11/14 , G11C11/15
CPC分类号： G11C11/16
摘要： In a method of programming a magneto resistive memory cell, a first magnetic field is applied to the magneto resistive memory cell. It is determined whether the magneto resistive memory cell meets a programming criterion. In case that the magneto resistive memory cell does not meet the programming criterion, a second magnetic field, which is higher or lower than the first magnetic field, is applied to the magneto resistive memory cell. It is then determined whether the magneto resistive memory cell meets a programming criterion. The magnetic field is increased or decreased in case that the magneto resistive memory cell does not meet the programming criterion until the magneto resistive memory cell meets the programming criterion.
摘要翻译：在编写磁阻存储器单元的方法中，第一磁场被施加到磁阻存储器单元。确定磁阻存储器单元是否满足编程标准。在磁阻存储器单元不满足编程标准的情况下，将高于或低于第一磁场的第二磁场施加到磁阻存储器单元。然后确定磁阻存储器单元是否满足编程标准。在磁阻存储器单元不满足编程标准直到磁阻存储器单元满足编程标准的情况下，磁场增加或减小。

8. 发明授权

US07161861B2 Sense amplifier bitline boost circuit 有权
标题翻译：感应放大器位线升压电路
公开(公告)号：US07161861B2
公开(公告)日：2007-01-09
申请号：US10988787
申请日：2004-11-15
申请人： Dietmar Gogl , Hans-Heinrich Viehmann
发明人： Dietmar Gogl , Hans-Heinrich Viehmann
IPC分类号： G11C7/02 , G11C7/00
CPC分类号： G11C5/145 , G11C7/06 , G11C7/12 , G11C11/16 , G11C2207/063
摘要： A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost circuit to shorten the charging time for parasitic circuit capacitance. The bitline boost circuit includes a source follower coupled to a reference voltage and a switch coupled to another voltage source. The switch is enabled to conduct during an initial period of sensing the resistance of the memory cell. The source follower in the bitline boost circuit is configured to clamp the voltage of an input signal at substantially the same level as the clamping devices, and to provide additional current to shorten the period for charging parasitic capacitance. The resulting current sense amplifier can be used to implement a memory device with fast and reliable read times and low manufacturing cost.
摘要翻译：包括钳位装置和电流镜的电流检测放大器被配置为使用位线升压电路感测MTJ存储器单元的电阻，以缩短寄生电路电容的充电时间。位线升压电路包括耦合到参考电压的源极跟随器和耦合到另一个电压源的开关。在感测存储单元的电阻的初始时段期间，该开关能够导通。位线升压电路中的源极跟随器被配置为将输入信号的电压钳位在与钳位装置基本相同的电平上，并提供额外的电流以缩短对寄生电容充电的周期。所得到的电流检测放大器可用于实现具有快速可靠的读取时间和低制造成本的存储器件。

9. 发明申请

US20060050584A1 Current sense amplifier 有权
标题翻译：电流检测放大器
公开(公告)号：US20060050584A1
公开(公告)日：2006-03-09
申请号：US10937155
申请日：2004-09-07
申请人： Dietmar Gogl , Hans-Heinrich Viehmann
发明人： Dietmar Gogl , Hans-Heinrich Viehmann
IPC分类号： G11C7/02
CPC分类号： G11C7/04 , G11C7/02 , G11C7/062 , G11C7/067 , G11C11/16 , G11C2207/063
摘要： A high-speed current sense amplifier has complementary reference cells and load devices that eliminate capacitive mismatch contributions. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal node. The first clamping device is coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal node. The second clamping device is also coupled to the reference voltage. A current mirror is coupled between the first and second input of the voltage comparator and is coupled to an active capacitance balancing circuit. The active capacitance balancing circuit may be combined with the voltage comparator. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal node and the second input signal node.
摘要翻译：高速电流检测放大器具有补充参考电池和负载器件，可消除电容失配的贡献。电流感测放大器包括电压比较器，耦合在电压比较器的第一输入端和第一输入信号节点之间的第一钳位装置。第一钳位装置耦合到参考电压。第二钳位装置耦合在电压比较器的第二输入端和第二输入信号节点之间。第二钳位装置也耦合到参考电压。电流镜耦合在电压比较器的第一和第二输入端之间并耦合到有源电容平衡电路。有源电容平衡电路可以与电压比较器组合。均衡器件可以耦合在电压比较器的第一和第二输入之间，以及第一输入信号节点和第二输入信号节点之间。

10. 发明授权

US07019554B2 Methods and apparatus for active termination of high-frequency signals 失效
标题翻译：主动终止高频信号的方法和装置
公开(公告)号：US07019554B2
公开(公告)日：2006-03-28
申请号：US10727106
申请日：2003-12-03
申请人： Oliver Kiehl , Hans-Heinrich Viehmann
发明人： Oliver Kiehl , Hans-Heinrich Viehmann
IPC分类号： H03K19/003
CPC分类号： H04L25/0298
摘要： An integrated circuit includes at least one main circuit 313 operable to perform one or more functions. At least one termination node DQ receives or transmits an operating signal. An active termination circuit 301 has first and second transistors of opposite type coupled in series between a Vdd node of a first source potential and a Vss node of a second source potential. The at least one termination node is coupled to a common node between the first and second transistors. A control circuit operates to bias the first and second transistors such that they exhibit a controlled impedance at the common node. Alternatively, the control circuit operates to bias the first and second transistors such that they provide a clamping function at the common node.
摘要翻译：集成电路包括至少一个可操作以执行一个或多个功能的主电路313。至少一个终端节点DQ接收或发送操作信号。有源终端电路301具有串联耦合在第一源电位的Vdd节点和第二源极电位的Vss节点之间的相反类型的第一和第二晶体管。至少一个终端节点耦合到第一和第二晶体管之间的公共节点。控制电路操作以偏置第一和第二晶体管，使得它们在公共节点处呈现受控阻抗。或者，控制电路操作以偏置第一和第二晶体管，使得它们在公共节点处提供钳位功能。

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