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1. 发明授权

US06807089B2 Method for operating an MRAM semiconductor memory configuration 失效
标题翻译：用于操作MRAM半导体存储器配置的方法
公开(公告)号：US06807089B2
公开(公告)日：2004-10-19
申请号：US10685082
申请日：2003-10-14
申请人： Dietmar Gogl , Till Schloesser
发明人： Dietmar Gogl , Till Schloesser
IPC分类号： G11C1100
CPC分类号： G11C11/15
摘要： In a method for operating an MRAM semiconductor memory configuration, for the purpose of reading an item of stored information, reversible magnetic changes are made to the TMR cell and a current that is momentarily altered as a result is compared with the original read signal. As a result, the TMR memory cell itself can serve as a reference, even though the information in the TMR memory cell is not destroyed, i.e. writing-back does not have to be effected. The method can preferably be applied to an MRAM memory configuration in which a plurality of TMR cells are connected, in parallel, to a selection transistor and in which there is a write line which is not electrically connected to the memory cell.
摘要翻译：在用于操作MRAM半导体存储器配置的方法中，为了读取存储的信息的项目，对TMR单元进行可逆的磁性改变，并且将与暂时改变的电流作为结果与原始读取信号进行比较。结果，TMR存储单元本身可以用作参考，即使TMR存储单元中的信息不被破坏，即不需要进行回写。该方法可以优选地应用于其中多个TMR单元并联连接到选择晶体管并且其中存在没有电连接到存储器单元的写入线的MRAM存储器配置。

2. 发明授权

US09484457B2 Vertical floating body storage transistors formed in bulk devices and having buried sense and word lines 有权
标题翻译：在体积器件中形成的垂直浮体存储晶体管，具有掩埋感和字线
公开(公告)号：US09484457B2
公开(公告)日：2016-11-01
申请号：US13404759
申请日：2012-02-24
申请人： Peter Baars , Till Schloesser
发明人： Peter Baars , Till Schloesser
IPC分类号： H01L21/74 , H01L29/78 , H01L27/108
CPC分类号： H01L29/7841 , H01L27/10802
摘要： A semiconductor device comprises a memory area including floating body transistors in the form of pillar structures, which are formed in a bulk architecture. The pillar structures may be appropriately addressed on the basis of a buried word line and a buried sense region or sense lines in combination with an appropriate bit line contact regime.
摘要翻译：半导体器件包括存储区域，该存储器区域包括柱状结构形式的浮体晶体管，其以体积结构形式形成。可以基于掩埋字线和掩埋感测区域或感测线路与适当的位线接触方式组合来适当地寻址支柱结构。

3. 发明授权

US09034753B2 Method of forming conductive contacts on a semiconductor device with embedded memory and the resulting device 有权
标题翻译：在具有嵌入式存储器的半导体器件上形成导电触点的方法以及所得到的器件
公开(公告)号：US09034753B2
公开(公告)日：2015-05-19
申请号：US13164272
申请日：2011-06-20
申请人： Till Schloesser , Peter Baars
发明人： Till Schloesser , Peter Baars
IPC分类号： H01L21/4763 , H01L27/108 , H01L21/768
CPC分类号： H01L27/10894 , H01L21/76816 , H01L21/76895 , H01L27/10814 , H01L27/10855 , H01L27/10888
摘要： A method is disclosed that includes forming a conductive logic contact in a logic area of a semiconductor device, forming a bit line contact and a capacitor contact in a memory array of the semiconductor device, and performing at least one first common process to form a first metallization layer comprising a first conductive line in the logic area that is conductively coupled to the conductive logic contact and a bit line in the memory array that is conductively coupled to the bit line contact. The method further includes performing at least one second common process to form a second metallization layer comprising a first conductive structure conductively coupled to the first conductive line in the logic area and a second conductive structure in the memory array that that is conductively coupled to the capacitor contact.
摘要翻译：公开了一种方法，其包括在半导体器件的逻辑区域中形成导电逻辑触点，在半导体器件的存储器阵列中形成位线接触和电容器触点，以及执行至少一个第一公共工艺以形成第一金属化层包括在逻辑区域中的导电耦合到导电逻辑触点的第一导线和存储器阵列中与导线耦合到位线触点的位线。所述方法还包括执行至少一个第二公共处理以形成第二金属化层，所述第二金属化层包括导电耦合到所述逻辑区域中的所述第一导电线的第一导电结构和所述存储器阵列中的导电耦合到所述电容器的第二导电结构联系。

4. 发明授权

US08722523B2 Semiconductor device comprising self-aligned contact elements and a replacement gate electrode structure 有权
标题翻译：半导体器件包括自对准接触元件和替换栅电极结构
公开(公告)号：US08722523B2
公开(公告)日：2014-05-13
申请号：US13371049
申请日：2012-02-10
申请人： Till Schloesser , Peter Baars , Frank Jakubowski
发明人： Till Schloesser , Peter Baars , Frank Jakubowski
IPC分类号： H01L29/772
CPC分类号： H01L29/78 , H01L21/28518 , H01L21/28525 , H01L21/288 , H01L21/76816 , H01L21/823412 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： When forming sophisticated semiconductor devices including high-k metal gate electrode structures, a raised drain and source configuration may be used for controlling the height upon performing a replacement gate approach, thereby providing superior conditions for forming contact elements and also obtaining a well-controllable reduced gate height.
摘要翻译：当形成包括高k金属栅电极结构的复杂半导体器件时，可以使用升高的漏极和源极配置来控制在执行替代栅极接近时的高度，从而为形成接触元件提供优越的条件，并且还获得良好可控的减小的门高。

5. 发明授权

US08598655B1 Semiconductor device and method for manufacturing a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08598655B1
公开(公告)日：2013-12-03
申请号：US13566742
申请日：2012-08-03
申请人： Till Schloesser , Rolf Weis , Ralf Rudolf
发明人： Till Schloesser , Rolf Weis , Ralf Rudolf
IPC分类号： H01L29/08 , H01L29/417 , H01L29/78
CPC分类号： H01L27/0883 , H01L21/823412 , H01L21/823487 , H01L29/0634 , H01L29/42368 , H01L29/7809 , H01L29/781 , H01L29/7813 , H01L29/7828 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first transistor with a first drift zone, and a plurality of second transistors, each second transistor comprising a source region, a drain region and a gate electrode. The second transistors are electrically coupled in series to form a series circuit that is electrically coupled to the first transistor, the first and the plurality of second transistors being at least partially disposed in a semiconductor substrate including a buried doped layer, wherein the source or the drain regions of the second transistors are disposed in the buried doped layer.
摘要翻译：半导体器件包括具有第一漂移区的第一晶体管和多个第二晶体管，每个第二晶体管包括源极区，漏极区和栅电极。第二晶体管串联电耦合以形成电耦合到第一晶体管的串联电路，第一和第二晶体管至少部分地设置在包括掩埋掺杂层的半导体衬底中，其中源极或第二晶体管的漏极区域设置在掩埋掺杂层中。

6. 发明申请

US20120280296A1 Semiconductor Device with DRAM Bit Lines Made From Same Material as Gate Electrodes in Non-Memory Regions of the Device, and Methods of Making Same 有权
标题翻译：具有与位于非存储器区域中的栅电极相同材料的DRAM位线的半导体器件及其制造方法
公开(公告)号：US20120280296A1
公开(公告)日：2012-11-08
申请号：US13099692
申请日：2011-05-03
申请人： Peter Baars , Till Schloesser , Frank Jakubowski
发明人： Peter Baars , Till Schloesser , Frank Jakubowski
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10894 , H01L27/10885
摘要： Generally, the present disclosure is directed to a semiconductor device with DRAM bit lines made from the same material as the gate electrodes in non-memory regions of the device, and methods of making the same. One illustrative method disclosed herein comprises forming a semiconductor device including a memory array and a logic region. The method further comprises forming a buried word line in the memory array and, after forming the buried word line, performing a first common process operation to form at least a portion of a conductive gate electrode in the logic region and to form at least a portion of a conductive bit line in the memory array.
摘要翻译：通常，本公开涉及一种具有由与器件的非存储区域中的栅电极相同的材料制成的DRAM位线的半导体器件及其制造方法。本文公开的一种说明性方法包括形成包括存储器阵列和逻辑区域的半导体器件。所述方法还包括在所述存储器阵列中形成掩埋字线，并且在形成所述掩埋字线之后，执行第一公共处理操作以形成所述逻辑区域中的导电栅电极的至少一部分并且形成至少一部分的存储器阵列中的导电位线。

7. 发明申请

US20120217612A1 VERTICAL FLOATING BODY STORAGE TRANSISTORS FORMED IN BULK DEVICES AND HAVING BURIED SENSE AND WORD LINES 有权
标题翻译：立体式浮体式存储晶体管，形成大容量设备，并具有传感器和字线
公开(公告)号：US20120217612A1
公开(公告)日：2012-08-30
申请号：US13404759
申请日：2012-02-24
申请人： Peter Baars , Till Schloesser
发明人： Peter Baars , Till Schloesser
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/7841 , H01L27/10802
摘要： A semiconductor device comprises a memory area including floating body transistors in the form of pillar structures, which are formed in a bulk architecture. The pillar structures may be appropriately addressed on the basis of a buried word line and a buried sense region or sense lines in combination with an appropriate bit line contact regime.
摘要翻译：半导体器件包括存储区域，该存储器区域包括柱状结构形式的浮体晶体管，其以体积结构形式形成。可以基于掩埋字线和掩埋感测区域或感测线路与适当的位线接触方式组合来适当地寻址支柱结构。

8. 发明授权

US07956387B2 Transistor and memory cell array 有权
标题翻译：晶体管和存储单元阵列
公开(公告)号：US07956387B2
公开(公告)日：2011-06-07
申请号：US11517558
申请日：2006-09-08
申请人： Till Schloesser
发明人： Till Schloesser
IPC分类号： H01L26/66 , H01L21/02
CPC分类号： H01L27/10891 , H01L27/10823 , H01L27/10876 , H01L27/11507
摘要： A transistor, which is formed in a semiconductor substrate having a top surface, includes first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode for controlling an electrical current flowing in the channel. The gate electrode is disposed in a lower portion of a gate groove defined in the top surface of the semiconductor substrate. The upper portion of the groove is filled with an insulating material. The channel includes a fin-like portion in the shape of a ridge having a top side and two lateral sides in a cross-section perpendicular to a direction defined by a line connecting the first and second source/drain regions. The gate electrode encloses the channel at the top side and the two lateral sides thereof.
摘要翻译：形成在具有顶表面的半导体衬底中的晶体管包括第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道以及用于控制在沟道中流动的电流的栅电极。栅电极设置在限定在半导体衬底的顶表面中的栅极沟槽的下部。槽的上部填充有绝缘材料。通道包括脊形状的翅片状部分，其具有垂直于由连接第一和第二源极/漏极区域的线限定的方向的横截面中的顶侧和两个侧面。栅电极在其顶侧和其两个侧面包围通道。

9. 发明授权

US07863149B2 Method for fabricating a capacitor 有权
标题翻译：制造电容器的方法
公开(公告)号：US07863149B2
公开(公告)日：2011-01-04
申请号：US11223800
申请日：2005-09-09
申请人： Srivatsa Kundalgurki , Peter Moll , Dirk Manger , Kristin Schupke , Till Schloesser
发明人： Srivatsa Kundalgurki , Peter Moll , Dirk Manger , Kristin Schupke , Till Schloesser
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： In a method for fabricating a capacitor that includes an electrode structure (80), an auxiliary layer (40) is formed over a substrate (10). A recess (60), which determines the shape of the electrode structure (80), is etched into the auxiliary layer (40), and the electrode structure of the capacitor is formed in the recess. As an example, the auxiliary layer can be a semiconductor layer (40).
摘要翻译：在制造包括电极结构（80）的电容器的方法中，辅助层（40）形成在衬底（10）上。确定电极结构（80）的形状的凹部（60）被蚀刻到辅助层（40）中，电容器的电极结构形成在凹部中。作为示例，辅助层可以是半导体层（40）。

10. 发明授权

US07772631B2 Method for fabricating a memory cell arrangement with a folded bit line arrangement and corresponding memory cell arrangement with a folded bit line arrangement 有权
标题翻译：用于制造具有折叠位线布置的存储单元布置和具有折叠位线布置的相应存储单元布置的方法
公开(公告)号：US07772631B2
公开(公告)日：2010-08-10
申请号：US11493082
申请日：2006-07-26
申请人： Till Schloesser
发明人： Till Schloesser
IPC分类号： H01L27/108
CPC分类号： H01L27/10891 , H01L27/10852 , H01L27/10897
摘要： An integrated circuit includes a memory cell arrangement with a plurality of active regions along a first direction, a plurality of parallel buried word lines (BWL) along a second direction, a plurality of parallel bitlines along a third direction, and a plurality of storage capacitors. The BWLs run through the active regions. Two of the BWLs are spaced apart from one another and from isolation trenches running through a respective active region, the BWLs being insulated from a channel region by a gate dielectric. The bit lines run perpendicular to the second direction, wherein each bit line makes contact with the relevant source region of the associated active region. The first direction lies between the second and third directions. Storage capacitors are connected to associated drain regions in a respective active region.
摘要翻译：集成电路包括具有沿着第一方向的多个有源区的存储单元布置，沿着第二方向的多个并行掩埋字线（BWL），沿着第三方向的多个平行位线，以及多个存储电容器。 BWL运行在活动区域。 BWL中的两个彼此间隔开，并且从穿过相应的有源区域的隔离沟槽间隔开，BWL通过栅极电介质与沟道区域绝缘。位线垂直于第二方向延伸，其中每个位线与相关联的有源区域的相关源极区域接触。第一个方向在第二和第三个方向之间。存储电容器连接到相应的有源区域中的相关联的漏极区域。

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