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1. 发明授权

US07396747B2 Hetero-integrated strained silicon n- and p-MOSFETs 有权
标题翻译：异质集成应变硅n和p-MOSFET
公开(公告)号：US07396747B2
公开(公告)日：2008-07-08
申请号：US11840029
申请日：2007-08-16
申请人： Diane C. Boyd , Juan Cai , Kevin K. Chan , Patricia M. Mooney , Kern Rim
发明人： Diane C. Boyd , Juan Cai , Kevin K. Chan , Patricia M. Mooney , Kern Rim
IPC分类号： H01L21/265 , H01L21/00 , H01L21/84
CPC分类号： H01L29/1054 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L29/7842 , Y10S438/938
摘要： The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.
摘要翻译：本发明提供半导体结构和制造用于施加MOSFET器件的这种结构的方法。以这样的方式制造半导体结构，使得制造n-MOSFET的晶片区域中的层结构不同于制造p-MOSFET的晶片的区域中的层结构。通过首先通过离子注入诸如He的光原子形成具有含Si衬底的表面的损伤区域来制造结构。然后在含有受损区域的含Si衬底上形成应变SiGe合金。然后采用退火步骤通过缺陷引发的应变弛豫引起应变SiGe合金的显着松弛。接下来，在弛豫的SiGe合金上形成诸如应变Si的应变半导体盖。

2. 发明申请

US20080251813A1 HETERO-INTEGRATED STRAINED SILICON n- AND p- MOSFETS 审中-公开
标题翻译： HETERO-INTEGRATED应变硅n-和p- MOSFET
公开(公告)号：US20080251813A1
公开(公告)日：2008-10-16
申请号：US12140612
申请日：2008-06-17
申请人： Diane C. Boyd , Juan Cai , Kevin K. Chan , Patricia M. Mooney , Kern Rim
发明人： Diane C. Boyd , Juan Cai , Kevin K. Chan , Patricia M. Mooney , Kern Rim
IPC分类号： H01L29/778
CPC分类号： H01L21/26506 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/26513 , H01L21/823807 , H01L29/1054 , H01L29/7842 , Y10S438/938
摘要： The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.
摘要翻译：本发明提供半导体结构和制造用于施加MOSFET器件的这种结构的方法。以这样的方式制造半导体结构，使得制造n-MOSFET的晶片区域中的层结构不同于制造p-MOSFET的晶片的区域中的层结构。通过首先通过离子注入诸如He的光原子形成具有含Si衬底的表面的损伤区域来制造结构。然后在含有受损区域的含Si衬底上形成应变SiGe合金。然后采用退火步骤通过缺陷引发的应变弛豫引起应变SiGe合金的显着松弛。接下来，在弛豫的SiGe合金上形成诸如应变Si的应变半导体盖。

3. 发明授权

US07273800B2 Hetero-integrated strained silicon n- and p-MOSFETs 有权
标题翻译：异质集成应变硅n和p-MOSFET
公开(公告)号：US07273800B2
公开(公告)日：2007-09-25
申请号：US10978715
申请日：2004-11-01
申请人： Diane C. Boyd , Juan Cai , Kevin K. Chan , Patricia M. Mooney , Kern Rim
发明人： Diane C. Boyd , Juan Cai , Kevin K. Chan , Patricia M. Mooney , Kern Rim
IPC分类号： H01L21/265 , H01L21/00 , H01L21/84
CPC分类号： H01L29/1054 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L29/7842 , Y10S438/938
摘要： The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.
摘要翻译：本发明提供半导体结构和制造用于施加MOSFET器件的这种结构的方法。以这样的方式制造半导体结构，使得制造n-MOSFET的晶片区域中的层结构不同于制造p-MOSFET的晶片的区域中的层结构。通过首先通过离子注入诸如He的光原子形成具有含Si衬底的表面的损伤区域来制造结构。然后在含有受损区域的含Si衬底上形成应变SiGe合金。然后采用退火步骤通过缺陷引发的应变弛豫引起应变SiGe合金的显着松弛。接下来，在弛豫的SiGe合金上形成诸如应变Si的应变半导体盖。

4. 发明授权

US06841831B2 Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process 有权
标题翻译：使用凹陷通道镶嵌栅极工艺，具有低源极和漏极电阻以及最小重叠电容的全耗尽SOI MOSFET
公开(公告)号：US06841831B2
公开(公告)日：2005-01-11
申请号：US10461821
申请日：2003-06-13
申请人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
发明人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
IPC分类号： H01L21/336 , H01L29/786 , H01L29/76
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78612
摘要： A sub-0.05 μm channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 μm channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.
摘要翻译：提供了具有低源极和漏极电阻以及最小重叠电容的0.05微米通道长度的全耗尽SOI MOSFET器件及其制造方法。子0.05通道长度全耗尽的SOI MOSFET器件包括SOI结构，其至少包含具有第一厚度的沟道区和邻接其中存在第二厚度的源极/漏极区的SOI层，其中第二厚度为大于第一厚度，并且源/漏区具有存在于其上的自对准硅化物层。栅极区也存在于SOI层的顶部。

5. 发明授权

US06660598B2 Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region 失效
标题翻译：形成具有稀疏沟道区的完全耗尽的SOI（绝缘体上硅）MOSFET的方法
公开(公告)号：US06660598B2
公开(公告)日：2003-12-09
申请号：US10084550
申请日：2002-02-26
申请人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
发明人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
IPC分类号： H01L21336
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78612
摘要： A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. In accordance with the method of the present invention, at least one dummy gate region is first formed atop an SOI layer. The dummy gate region includes at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of the sacrificial polysilicon region. Next, an oxide layer that is coplanar with an upper surface of the dummy gate region is formed and then the sacrificial polysilicon region is removed to expose a portion of the SOI layer. A thinned device channel region is formed in the exposed portion of the SOI layer and thereafter inner nitride spacers are formed on exposed walls of the fist nitride spacers. Next, a gate region is formed over the thinned device channel region and then the oxide layer is removed so as to expose thicker portions of the SOI layer than de device channel region.
摘要翻译：提供了具有低源极和漏极电阻以及最小重叠电容的0.05微米通道长度的全耗尽SOI MOSFET器件及其制造方法。根据本发明的方法，首先在SOI层顶部形成至少一个虚拟栅极区域。虚拟栅极区域至少包括牺牲多晶硅区域和位于牺牲多晶硅区域的侧壁上的第一氮化物间隔物。接下来，形成与伪栅极区的上表面共面的氧化物层，然后除去牺牲多晶硅区域，以露出SOI层的一部分。在SOI层的暴露部分中形成一个变薄的器件沟道区，此后在第一氮化物间隔物的暴露的壁上形成内部氮化物间隔物。接下来，在减薄的器件沟道区上形成栅极区，然后除去氧化物层，以便暴露出SOI层的比较器件沟道区更厚的部分。

6. 发明申请

US20080254622A1 CMOS SILICIDE METAL GATE INTEGRATION 失效
标题翻译： CMOS硅胶金属门整合
公开(公告)号：US20080254622A1
公开(公告)日：2008-10-16
申请号：US12145113
申请日：2008-06-24
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译：本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

7. 发明授权

US07002214B1 Ultra-thin body super-steep retrograde well (SSRW) FET devices 有权
标题翻译：超薄体超陡逆行井（SSRW）FET器件
公开(公告)号：US07002214B1
公开(公告)日：2006-02-21
申请号：US10710736
申请日：2004-07-30
申请人： Diane C. Boyd , Judson R. Holt , MeiKei Ieong , Renee T. Mo , Zhibin Ren , Ghavam G. Shahidi
发明人： Diane C. Boyd , Judson R. Holt , MeiKei Ieong , Renee T. Mo , Zhibin Ren , Ghavam G. Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/823892 , H01L21/84 , H01L29/66772 , H01L29/78609 , H01L29/78618 , H01L29/78696
摘要： A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.
摘要翻译：超陡逆行井场效应晶体管器件的制造方法从形成在衬底上的SOI层开始。掩埋氧化层。使SOI层变薄以形成超薄SOI层。形成将SOI层分离成N和P接地平面区域的隔离沟槽。用高水平的N型和P型掺杂剂掺杂由SOI层形成的N和P接地平面区域。在N和P接地平面区域之上形成半导体沟道区。在沟道区域上方形成FET源极和漏极区域以及栅极电极堆叠。可选地，在SOI接地平面区域和沟道区域之间形成扩散延迟层。

8. 发明授权

US06762469B2 High performance CMOS device structure with mid-gap metal gate 失效
标题翻译：高性能CMOS器件结构，具有中间间隙金属栅极
公开(公告)号：US06762469B2
公开(公告)日：2004-07-13
申请号：US10127196
申请日：2002-04-19
申请人： Anda C. Mocuta , Meikei Ieong , Ricky S. Amos , Diane C. Boyd , Dan M. Mocuta , Huajie Chen
发明人： Anda C. Mocuta , Meikei Ieong , Ricky S. Amos , Diane C. Boyd , Dan M. Mocuta , Huajie Chen
IPC分类号： H01L2976
CPC分类号： H01L21/823807 , H01L21/823828
摘要： High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.
摘要翻译：公开了具有中间间隙功函数金属栅极的高性能（表面沟道）CMOS器件，其中外延层用于PFET区域的阈值电压Vt调整/减小，用于大的Vt降低（〜500mV），如需要具有中间间隙金属栅极的CMOS器件。本发明提供了使用原位B掺杂外延层或B和C共掺杂外延层的反掺杂，其中C共掺杂提供了额外的自由度以减少B的扩散（也在随后的激活热循环期间））以保持浅的B剖面，这对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是至关重要的，同时保持良好的短沟道效应。对于具有中间间隙金属栅极的器件，B扩散曲线令人满意地浅，尖锐且具有高B浓度，以在栅极氧化物下提供并保持薄的高掺杂B层。

9. 发明授权

US06461529B1 Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme 失效
标题翻译：各向异性氮化物蚀刻工艺，在镶嵌蚀刻方案中对氧化物和光致抗蚀剂层具有高选择性
公开(公告)号：US06461529B1
公开(公告)日：2002-10-08
申请号：US09299137
申请日：1999-04-26
申请人： Diane C. Boyd , Stuart M. Burns , Hussein I. Hanafi , Waldemar W. Kocon , William C. Wille , Richard Wise
发明人： Diane C. Boyd , Stuart M. Burns , Hussein I. Hanafi , Waldemar W. Kocon , William C. Wille , Richard Wise
IPC分类号： H01L213215
CPC分类号： H01L29/66583 , H01L21/31116 , H01L21/76224 , H01L21/823481
摘要： A process and etchant gas composition for anisotropically etching a trench in a silicon nitride layer of a multilayer structure. The etchant gas composition has an etchant gas including a polymerizing agent, a hydrogen source, an oxidant, and a noble gas diluent. The oxidant preferably includes a carbon-containing oxidant component and an oxidant-noble gas component. The fluorocarbon gas is selected from CF4, C2F6, and C3F8; the hydrogen source is selected from CHF3, CH2F2, CH3F, and H2; the oxidant is selected from CO, CO2, and O2; and the noble gas diluent is selected from He, Ar, and Ne. The constituents are added in amounts to achieve an etchant gas having a high nitride selectivity to silicon oxide and photoresist. A power source, such as an RF power source, is applied to the structure to control the directionality of the high density plasma formed by exciting the etchant gas. The power source that controls the directionality of the plasma is decoupled from the power source used to excite the etchant gas. The etchant gas can be used during a nitride etch step in a process for making a metal oxide semiconductor field effect transistor.
摘要翻译：一种用于各向异性蚀刻多层结构的氮化硅层中的沟槽的工艺和蚀刻剂气体组合物。蚀刻剂气体组合物具有包括聚合剂，氢源，氧化剂和惰性气体稀释剂的蚀刻剂气体。氧化剂优选包括含碳氧化剂组分和氧化剂 - 惰性气体组分。碳氟化合物气体选自CF4，C2F6和C3F8; 氢源选自CHF 3，CH 2 F 2，CH 3 F和H 2; 氧化剂选自CO，CO 2和O 2; 惰性气体稀释剂选自He，Ar和Ne。添加成分以达到对氧化硅和光致抗蚀剂具有高氮化物选择性的蚀刻剂气体。将诸如RF电源的电源施加到结构以控制通过激发蚀刻剂气体形成的高密度等离子体的方向性。控制等离子体方向性的电源与用于激发蚀刻剂气体的电源脱耦。在制造金属氧化物半导体场效应晶体管的工艺中的氮化物蚀刻步骤期间可以使用蚀刻剂气体。

10. 发明授权

US06221562B1 Resist image reversal by means of spun-on-glass 失效
标题翻译：通过旋转玻璃抵抗图像反转
公开(公告)号：US06221562B1
公开(公告)日：2001-04-24
申请号：US09192137
申请日：1998-11-13
申请人： Diane C. Boyd , Toshiharu Furukawa , Steven J. Holmes , William H. Ma , Paul A. Rabidoux , David V. Horak
发明人： Diane C. Boyd , Toshiharu Furukawa , Steven J. Holmes , William H. Ma , Paul A. Rabidoux , David V. Horak
IPC分类号： G03F700
CPC分类号： H01L21/0337 , G03F7/40 , H01L21/0274 , H01L21/32139
摘要： An image reversal method of turning hybrid photoresist spaces into resist lines for sub-feature size applications. The sub-feature size space width of the high resolution hybrid photoresist is largely independent of the lithographic process and mask reticles. These sub-feature size spaces formed by the hybrid resist are then turned into sub-feature size lines using Spin-On-Glass, SOG. The SOG is first coated over the entire patterned hybrid resist to fill in the hybrid spaces and cover the photoresist. SOG is then recessed back to expose the photoresist layer. The exposed photoresist is then removed. The sub-feature size lines are then left behind as a mask to pattern the same onto the underlying films on the substrate.
摘要翻译：将混合光致抗蚀剂空间转换成用于子特征尺寸应用的抗蚀剂线的图像反转方法。高分辨率混合光致抗蚀剂的子特征尺寸空间宽度在很大程度上独立于光刻工艺和掩模掩模版。然后，使用旋转玻璃，SOG将由混合抗蚀剂形成的这些子特征尺寸空间变成子特征尺寸线。 SOG首先涂覆在整个图案化的混合抗蚀剂上以填充混合空间并覆盖光致抗蚀剂。然后将SOG凹进来露出光致抗蚀剂层。然后除去曝光的光致抗蚀剂。然后将子特征尺寸线作为掩模留下以将其图案化到衬底上的下面的膜上。

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