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1. 发明授权

US07002214B1 Ultra-thin body super-steep retrograde well (SSRW) FET devices 有权
标题翻译：超薄体超陡逆行井（SSRW）FET器件
公开(公告)号：US07002214B1
公开(公告)日：2006-02-21
申请号：US10710736
申请日：2004-07-30
申请人： Diane C. Boyd , Judson R. Holt , MeiKei Ieong , Renee T. Mo , Zhibin Ren , Ghavam G. Shahidi
发明人： Diane C. Boyd , Judson R. Holt , MeiKei Ieong , Renee T. Mo , Zhibin Ren , Ghavam G. Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/823892 , H01L21/84 , H01L29/66772 , H01L29/78609 , H01L29/78618 , H01L29/78696
摘要： A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.
摘要翻译：超陡逆行井场效应晶体管器件的制造方法从形成在衬底上的SOI层开始。掩埋氧化层。使SOI层变薄以形成超薄SOI层。形成将SOI层分离成N和P接地平面区域的隔离沟槽。用高水平的N型和P型掺杂剂掺杂由SOI层形成的N和P接地平面区域。在N和P接地平面区域之上形成半导体沟道区。在沟道区域上方形成FET源极和漏极区域以及栅极电极堆叠。可选地，在SOI接地平面区域和沟道区域之间形成扩散延迟层。

2. 发明授权

US06762469B2 High performance CMOS device structure with mid-gap metal gate 失效
标题翻译：高性能CMOS器件结构，具有中间间隙金属栅极
公开(公告)号：US06762469B2
公开(公告)日：2004-07-13
申请号：US10127196
申请日：2002-04-19
申请人： Anda C. Mocuta , Meikei Ieong , Ricky S. Amos , Diane C. Boyd , Dan M. Mocuta , Huajie Chen
发明人： Anda C. Mocuta , Meikei Ieong , Ricky S. Amos , Diane C. Boyd , Dan M. Mocuta , Huajie Chen
IPC分类号： H01L2976
CPC分类号： H01L21/823807 , H01L21/823828
摘要： High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.
摘要翻译：公开了具有中间间隙功函数金属栅极的高性能（表面沟道）CMOS器件，其中外延层用于PFET区域的阈值电压Vt调整/减小，用于大的Vt降低（〜500mV），如需要具有中间间隙金属栅极的CMOS器件。本发明提供了使用原位B掺杂外延层或B和C共掺杂外延层的反掺杂，其中C共掺杂提供了额外的自由度以减少B的扩散（也在随后的激活热循环期间））以保持浅的B剖面，这对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是至关重要的，同时保持良好的短沟道效应。对于具有中间间隙金属栅极的器件，B扩散曲线令人满意地浅，尖锐且具有高B浓度，以在栅极氧化物下提供并保持薄的高掺杂B层。

3. 发明授权

US06916698B2 High performance CMOS device structure with mid-gap metal gate 失效
标题翻译：高性能CMOS器件结构，具有中间间隙金属栅极
公开(公告)号：US06916698B2
公开(公告)日：2005-07-12
申请号：US10795672
申请日：2004-03-08
申请人： Anda C. Mocuta , Meikei Ieong , Ricky S. Amos , Diane C. Boyd , Dan M. Mocuta , Huajie Chen
发明人： Anda C. Mocuta , Meikei Ieong , Ricky S. Amos , Diane C. Boyd , Dan M. Mocuta , Huajie Chen
IPC分类号： H01L29/423 , H01L21/8238 , H01L27/092 , H01L29/49
CPC分类号： H01L21/823807 , H01L21/823828
摘要： High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.
摘要翻译：公开了具有中间间隙功函数金属栅极的高性能（表面沟道）CMOS器件，其中外延层用于PFET区域的阈值电压Vt调整/减小，用于大的Vt降低（〜500mV），如需要具有中间间隙金属栅极的CMOS器件。本发明提供了使用原位B掺杂外延层或B和C共掺杂外延层的反掺杂，其中C共掺杂提供了额外的自由度以减少B的扩散（也在随后的激活热循环期间））以保持浅的B剖面，这对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是至关重要的，同时保持良好的短沟道效应。对于具有中间间隙金属栅极的器件，B扩散曲线令人满意地浅，尖锐且具有高B浓度，以在栅极氧化物下提供并保持薄的高掺杂B层。

4. 发明授权

US07247569B2 Ultra-thin Si MOSFET device structure and method of manufacture 失效
标题翻译：超薄Si MOSFET器件结构及制造方法
公开(公告)号：US07247569B2
公开(公告)日：2007-07-24
申请号：US10725848
申请日：2003-12-02
申请人： Diane C. Boyd , Bruce B. Doris , Meikei Ieong , Devendra K. Sadana
发明人： Diane C. Boyd , Bruce B. Doris , Meikei Ieong , Devendra K. Sadana
IPC分类号： H01L21/302
CPC分类号： H01L21/28194 , H01L21/26533 , H01L21/28202 , H01L29/1083 , H01L29/49 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/78
摘要： The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a channel via atop the pad stack; providing a localized oxide region in the SOI layer on top of the buried insulating layer thereby thinning a portion of the SOI layer, the localized oxide region being self-aligned with the channel via; forming a gate in the channel via; removing at least the block mask; and forming source/drain extensions in the SOI layer abutting the thinned portion of the SOI layer. Providing the localized oxide region further comprises implanting oxygen dopant through the channel via into a portion of the SOI layer; and annealing the dopant to create the localized oxide region.
摘要翻译：本发明包括用于形成超薄沟道MOSFET的方法和由其制造的超薄沟道MOSFET。具体地说，该方法包括：在SOI层的下方提供具有掩埋绝缘层的SOI衬底; 在SOI层顶上形成焊盘堆叠; 通过所述垫堆叠的顶部形成具有通道的块掩模; 在所述掩埋绝缘层的顶部上的所述SOI层中提供局部氧化物区域，从而使所述SOI层的一部分变薄，所述局部氧化物区域与所述沟道通孔自对准; 在通道通道中形成一个门; 至少去除阻挡掩模; 以及在与SOI层的薄化部分邻接的SOI层中形成源极/漏极延伸部。提供局部氧化物区域还包括通过沟道通孔将氧掺杂剂注入到SOI层的一部分中; 并退火掺杂剂以产生局部氧化物区域。

5. 发明授权

US06911383B2 Hybrid planar and finFET CMOS devices 失效
标题翻译：混合平面和finFET CMOS器件
公开(公告)号：US06911383B2
公开(公告)日：2005-06-28
申请号：US10604097
申请日：2003-06-26
申请人： Bruce B. Doris , Diane C. Boyd , Meikei Ieong , Thomas S. Kanarsky , Jakub T. Kedzierski , Min Yang
发明人： Bruce B. Doris , Diane C. Boyd , Meikei Ieong , Thomas S. Kanarsky , Jakub T. Kedzierski , Min Yang
IPC分类号： H01L29/423 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/49 , H01L29/786 , H01L21/3205
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.
摘要翻译：本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上，绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。还提供了一种形成集成电路的方法。在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

6. 发明授权

US07482243B2 Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique 失效
标题翻译：超薄Si沟道MOSFET采用自对准氧注入和镶嵌技术
公开(公告)号：US07482243B2
公开(公告)日：2009-01-27
申请号：US11436756
申请日：2006-05-18
申请人： Diane C. Boyd , Bruce B. Doris , Meikei Ieong , Devendra K. Sadana
发明人： Diane C. Boyd , Bruce B. Doris , Meikei Ieong , Devendra K. Sadana
IPC分类号： H01L21/76 , H01L21/338 , H01L21/84 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78609 , H01L29/78684
摘要： The present invention provides a method of forming a thin channel MOSFET having low external resistance. The method comprises forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.
摘要翻译：本发明提供一种形成具有低外部电阻的薄沟道MOSFET的方法。该方法包括在基板的顶部形成伪栅极区域; 通过所述伪栅极注入形成氧化物的掺杂剂，以在与沟道区域的伪栅极区对准的衬底的一部分中产生局部氧化物区域; 形成邻接所述沟道区的源/漏扩展区; 并用栅极导体代替虚拟栅极。

7. 发明授权

US07075150B2 Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique 有权
公开(公告)号：US07075150B2
公开(公告)日：2006-07-11
申请号：US10725849
申请日：2003-12-02
申请人： Diane C. Boyd , Bruce B. Doris , Meikei Ieong , Devendra K. Sadana
发明人： Diane C. Boyd , Bruce B. Doris , Meikei Ieong , Devendra K. Sadana
IPC分类号： H01L27/01
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78609 , H01L29/78684
摘要： The present invention provides a thin channel MOSFET having low external resistance. In broad terms, a silicon-on-insulator structure comprising a SOI layer located atop a buried insulating layer, said SOI layer having a channel region which is thinned by the presence of an underlying localized oxide region that is located on top of and in contact with said buried insulating layer; and a gate region located atop said SOI layer, wherein said localized oxide region is self-aligned with the gate region. A method for forming the inventive MOSFET is also provided comprising forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.

8. 发明申请

US20080254622A1 CMOS SILICIDE METAL GATE INTEGRATION 失效
标题翻译： CMOS硅胶金属门整合
公开(公告)号：US20080254622A1
公开(公告)日：2008-10-16
申请号：US12145113
申请日：2008-06-24
申请人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
发明人： Ricky S. Amos , Diane C. Boyd , Cyril Cabral , Richard D. Kaplan , Jakub T. Kedzierski , Victor Ku , Woo-Hyeong Lee , Ying Li , Anda C. Mocuta , Vijay Narayanan , An L. Steegen , Maheswaren Surendra
IPC分类号： H01L21/44
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L29/66545 , H01L29/6656
摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.
摘要翻译：本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

9. 发明授权

US06461529B1 Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme 失效
标题翻译：各向异性氮化物蚀刻工艺，在镶嵌蚀刻方案中对氧化物和光致抗蚀剂层具有高选择性
公开(公告)号：US06461529B1
公开(公告)日：2002-10-08
申请号：US09299137
申请日：1999-04-26
申请人： Diane C. Boyd , Stuart M. Burns , Hussein I. Hanafi , Waldemar W. Kocon , William C. Wille , Richard Wise
发明人： Diane C. Boyd , Stuart M. Burns , Hussein I. Hanafi , Waldemar W. Kocon , William C. Wille , Richard Wise
IPC分类号： H01L213215
CPC分类号： H01L29/66583 , H01L21/31116 , H01L21/76224 , H01L21/823481
摘要： A process and etchant gas composition for anisotropically etching a trench in a silicon nitride layer of a multilayer structure. The etchant gas composition has an etchant gas including a polymerizing agent, a hydrogen source, an oxidant, and a noble gas diluent. The oxidant preferably includes a carbon-containing oxidant component and an oxidant-noble gas component. The fluorocarbon gas is selected from CF4, C2F6, and C3F8; the hydrogen source is selected from CHF3, CH2F2, CH3F, and H2; the oxidant is selected from CO, CO2, and O2; and the noble gas diluent is selected from He, Ar, and Ne. The constituents are added in amounts to achieve an etchant gas having a high nitride selectivity to silicon oxide and photoresist. A power source, such as an RF power source, is applied to the structure to control the directionality of the high density plasma formed by exciting the etchant gas. The power source that controls the directionality of the plasma is decoupled from the power source used to excite the etchant gas. The etchant gas can be used during a nitride etch step in a process for making a metal oxide semiconductor field effect transistor.
摘要翻译：一种用于各向异性蚀刻多层结构的氮化硅层中的沟槽的工艺和蚀刻剂气体组合物。蚀刻剂气体组合物具有包括聚合剂，氢源，氧化剂和惰性气体稀释剂的蚀刻剂气体。氧化剂优选包括含碳氧化剂组分和氧化剂 - 惰性气体组分。碳氟化合物气体选自CF4，C2F6和C3F8; 氢源选自CHF 3，CH 2 F 2，CH 3 F和H 2; 氧化剂选自CO，CO 2和O 2; 惰性气体稀释剂选自He，Ar和Ne。添加成分以达到对氧化硅和光致抗蚀剂具有高氮化物选择性的蚀刻剂气体。将诸如RF电源的电源施加到结构以控制通过激发蚀刻剂气体形成的高密度等离子体的方向性。控制等离子体方向性的电源与用于激发蚀刻剂气体的电源脱耦。在制造金属氧化物半导体场效应晶体管的工艺中的氮化物蚀刻步骤期间可以使用蚀刻剂气体。

10. 发明授权

US07396747B2 Hetero-integrated strained silicon n- and p-MOSFETs 有权
标题翻译：异质集成应变硅n和p-MOSFET
公开(公告)号：US07396747B2
公开(公告)日：2008-07-08
申请号：US11840029
申请日：2007-08-16
申请人： Diane C. Boyd , Juan Cai , Kevin K. Chan , Patricia M. Mooney , Kern Rim
发明人： Diane C. Boyd , Juan Cai , Kevin K. Chan , Patricia M. Mooney , Kern Rim
IPC分类号： H01L21/265 , H01L21/00 , H01L21/84
CPC分类号： H01L29/1054 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L29/7842 , Y10S438/938
摘要： The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.
摘要翻译：本发明提供半导体结构和制造用于施加MOSFET器件的这种结构的方法。以这样的方式制造半导体结构，使得制造n-MOSFET的晶片区域中的层结构不同于制造p-MOSFET的晶片的区域中的层结构。通过首先通过离子注入诸如He的光原子形成具有含Si衬底的表面的损伤区域来制造结构。然后在含有受损区域的含Si衬底上形成应变SiGe合金。然后采用退火步骤通过缺陷引发的应变弛豫引起应变SiGe合金的显着松弛。接下来，在弛豫的SiGe合金上形成诸如应变Si的应变半导体盖。

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