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1. 发明授权

US06841831B2 Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process 有权
标题翻译：使用凹陷通道镶嵌栅极工艺，具有低源极和漏极电阻以及最小重叠电容的全耗尽SOI MOSFET
公开(公告)号：US06841831B2
公开(公告)日：2005-01-11
申请号：US10461821
申请日：2003-06-13
申请人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
发明人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
IPC分类号： H01L21/336 , H01L29/786 , H01L29/76
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78612
摘要： A sub-0.05 μm channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 μm channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.
摘要翻译：提供了具有低源极和漏极电阻以及最小重叠电容的0.05微米通道长度的全耗尽SOI MOSFET器件及其制造方法。子0.05通道长度全耗尽的SOI MOSFET器件包括SOI结构，其至少包含具有第一厚度的沟道区和邻接其中存在第二厚度的源极/漏极区的SOI层，其中第二厚度为大于第一厚度，并且源/漏区具有存在于其上的自对准硅化物层。栅极区也存在于SOI层的顶部。

2. 发明授权

US06660598B2 Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region 失效
标题翻译：形成具有稀疏沟道区的完全耗尽的SOI（绝缘体上硅）MOSFET的方法
公开(公告)号：US06660598B2
公开(公告)日：2003-12-09
申请号：US10084550
申请日：2002-02-26
申请人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
发明人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
IPC分类号： H01L21336
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78612
摘要： A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. In accordance with the method of the present invention, at least one dummy gate region is first formed atop an SOI layer. The dummy gate region includes at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of the sacrificial polysilicon region. Next, an oxide layer that is coplanar with an upper surface of the dummy gate region is formed and then the sacrificial polysilicon region is removed to expose a portion of the SOI layer. A thinned device channel region is formed in the exposed portion of the SOI layer and thereafter inner nitride spacers are formed on exposed walls of the fist nitride spacers. Next, a gate region is formed over the thinned device channel region and then the oxide layer is removed so as to expose thicker portions of the SOI layer than de device channel region.
摘要翻译：提供了具有低源极和漏极电阻以及最小重叠电容的0.05微米通道长度的全耗尽SOI MOSFET器件及其制造方法。根据本发明的方法，首先在SOI层顶部形成至少一个虚拟栅极区域。虚拟栅极区域至少包括牺牲多晶硅区域和位于牺牲多晶硅区域的侧壁上的第一氮化物间隔物。接下来，形成与伪栅极区的上表面共面的氧化物层，然后除去牺牲多晶硅区域，以露出SOI层的一部分。在SOI层的暴露部分中形成一个变薄的器件沟道区，此后在第一氮化物间隔物的暴露的壁上形成内部氮化物间隔物。接下来，在减薄的器件沟道区上形成栅极区，然后除去氧化物层，以便暴露出SOI层的比较器件沟道区更厚的部分。

3. 发明授权

US07442612B2 Nitride-encapsulated FET (NNCFET) 有权
标题翻译：氮化物封装的FET（NNCFET）
公开(公告)号：US07442612B2
公开(公告)日：2008-10-28
申请号：US11481532
申请日：2006-07-06
申请人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
发明人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。在本发明中，提供自对准隔离区以减小DGFET结构中的寄生电容。此外，本发明封装了含硅沟道层，使背栅能够被更大程度地氧化，从而进一步降低结构的寄生电容。

4. 发明授权

US07214972B2 Strained silicon-channel MOSFET using a damascene gate process 失效
标题翻译：应变硅沟道MOSFET使用镶嵌栅极工艺
公开(公告)号：US07214972B2
公开(公告)日：2007-05-08
申请号：US11113858
申请日：2005-04-25
申请人： Hussein I. Hanafi , David J. Frank , Kevin K. Chan
发明人： Hussein I. Hanafi , David J. Frank , Kevin K. Chan
IPC分类号： H01L31/00
CPC分类号： H01L29/66545 , H01L29/665 , H01L29/66537 , H01L29/7842 , Y10S438/938
摘要： A metal oxide semiconductor field effect transistor (MOSFET) device is provided that includes a localized strained device channel and adjoining source/drain junctions that are unstrained. The MOSFET device has a very high channel carrier mobility, while maintaining a very low leakage junction.
摘要翻译：提供了一种金属氧化物半导体场效应晶体管（MOSFET）器件，其包括局部应变器件沟道和不受约束的邻接源极/漏极结。 MOSFET器件具有非常高的沟道载流子迁移率，同时保持非常低的泄漏结。

5. 发明授权

US07648880B2 Nitride-encapsulated FET (NNCFET) 失效
标题翻译：氮化物封装的FET（NNCFET）
公开(公告)号：US07648880B2
公开(公告)日：2010-01-19
申请号：US12142394
申请日：2008-06-19
申请人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
发明人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。在本发明中，提供自对准隔离区以减小DGFET结构中的寄生电容。此外，本发明封装了含硅沟道层，使背栅能够被更大程度地氧化，从而进一步降低结构的寄生电容。

6. 发明授权

US06916694B2 Strained silicon-channel MOSFET using a damascene gate process 失效
标题翻译：应变硅沟道MOSFET使用镶嵌栅极工艺
公开(公告)号：US06916694B2
公开(公告)日：2005-07-12
申请号：US10650400
申请日：2003-08-28
申请人： Hussein I. Hanafi , David J. Frank , Kevin K. Chan
发明人： Hussein I. Hanafi , David J. Frank , Kevin K. Chan
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L29/66545 , H01L29/665 , H01L29/66537 , H01L29/7842 , Y10S438/938
摘要： The present invention provides a method using a damascene-gate process to improve the transport properties of FETs through strain Si. Changes in mobility and FET characteristics are deliberately made in a Si or silicon-on-insulator (SOI) structure through the introduction of local strain in the channel region, without introducing strain in the device source and drain regions. The method has the advantage of not straining the source and drain regions resulting in very low leakage junctions and also it does not require any special substrate preparation like the case of a strained Si/relaxed SiGe system. Moreover, the method is compatible with existing mainstream CMOS processing. The present invention also provides a CMOS device that has a localized strained Si channel that is formed using the method of the present invention.
摘要翻译：本发明提供了一种使用镶嵌栅极工艺来改善FET通过应变Si的传输特性的方法。迁移率和FET特性的变化是通过在沟道区域中引入局部应变而在Si或绝缘体上硅（SOI）结构中作出的，而不会在器件源极和漏极区域引入应变。该方法的优点是不会使源极和漏极区域产生非常低的泄漏接头，并且也不需要像应变Si /弛豫SiGe系统那样的任何特殊的衬底制备。此外，该方法与现有的主流CMOS处理兼容。本发明还提供一种CMOS器件，其具有使用本发明的方法形成的局部应变Si沟道。

7. 发明授权

US07078773B2 Nitride-encapsulated FET (NNCFET) 失效
标题翻译：氮化物封装的FET（NNCFET）
公开(公告)号：US07078773B2
公开(公告)日：2006-07-18
申请号：US10328258
申请日：2002-12-23
申请人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
发明人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。在本发明中，提供自对准隔离区以减小DGFET结构中的寄生电容。此外，本发明封装了含硅沟道层，使背栅能够被更大程度地氧化，从而进一步降低结构的寄生电容。

8. 发明申请

US20080286930A1 NITRIDE-ENCAPSULATED FET (NNCFET) 失效
标题翻译：氮化物封装FET（NNCFET）
公开(公告)号：US20080286930A1
公开(公告)日：2008-11-20
申请号：US12142394
申请日：2008-06-19
申请人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
发明人： Kevin K. Chan , Hussein I. Hanafi , Paul M. Solomon
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.
摘要翻译：提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。在本发明中，提供自对准隔离区以减小DGFET结构中的寄生电容。此外，本发明封装了含硅沟道层，使背栅能够被更大程度地氧化，从而进一步降低结构的寄生电容。

9. 发明申请

US20080251813A1 HETERO-INTEGRATED STRAINED SILICON n- AND p- MOSFETS 审中-公开
标题翻译： HETERO-INTEGRATED应变硅n-和p- MOSFET
公开(公告)号：US20080251813A1
公开(公告)日：2008-10-16
申请号：US12140612
申请日：2008-06-17
申请人： Diane C. Boyd , Juan Cai , Kevin K. Chan , Patricia M. Mooney , Kern Rim
发明人： Diane C. Boyd , Juan Cai , Kevin K. Chan , Patricia M. Mooney , Kern Rim
IPC分类号： H01L29/778
CPC分类号： H01L21/26506 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/26513 , H01L21/823807 , H01L29/1054 , H01L29/7842 , Y10S438/938
摘要： The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.
摘要翻译：本发明提供半导体结构和制造用于施加MOSFET器件的这种结构的方法。以这样的方式制造半导体结构，使得制造n-MOSFET的晶片区域中的层结构不同于制造p-MOSFET的晶片的区域中的层结构。通过首先通过离子注入诸如He的光原子形成具有含Si衬底的表面的损伤区域来制造结构。然后在含有受损区域的含Si衬底上形成应变SiGe合金。然后采用退火步骤通过缺陷引发的应变弛豫引起应变SiGe合金的显着松弛。接下来，在弛豫的SiGe合金上形成诸如应变Si的应变半导体盖。

10. 发明授权

US07485518B2 Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) 失效
标题翻译：拉伸应变SiGe绝缘体上的应变Si MOSFET（SGOI）
公开(公告)号：US07485518B2
公开(公告)日：2009-02-03
申请号：US11684855
申请日：2007-03-12
申请人： Kevin K. Chan , Jack Q Chan , Kern Rim , Leathen Shi
发明人： Kevin K. Chan , Jack Q Chan , Kern Rim , Leathen Shi
IPC分类号： H01L21/336
CPC分类号： H01L29/78687 , H01L21/2007 , H01L29/1054 , H01L29/517 , H01L29/66742 , H01L29/7833 , H01L29/7842 , H01L29/78603
摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.
摘要翻译：提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。

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