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1. 发明授权

US09672019B2 Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads 有权
公开(公告)号：US09672019B2
公开(公告)日：2017-06-06
申请号：US12978557
申请日：2010-12-25
申请人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
发明人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
IPC分类号： G06F9/45 , G06F9/38 , G06F9/54 , G06F11/36
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

2. 发明申请

US20110167416A1 SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTEM TO AUTOMATICALLY DECOMPOSE A PROGRAM TO MULTIPLE PARALLEL THREADS 有权
标题翻译：用于硬件和软件系统的系统，设备和方法，用于自动将程序分解成多个并行线程
公开(公告)号：US20110167416A1
公开(公告)日：2011-07-07
申请号：US12978557
申请日：2010-12-25
申请人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
发明人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
IPC分类号： G06F9/45
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
摘要翻译：描述了用于将程序自动分解为多个并行线程的硬件和软件系统的系统，装置和方法。在一些实施例中，系统和装置执行原始代码分解和/或生成的线程执行的方法。

3. 发明授权

US07188234B2 Run-ahead program execution with value prediction 失效
标题翻译：带有价值预测的预测程序执行
公开(公告)号：US07188234B2
公开(公告)日：2007-03-06
申请号：US10017793
申请日：2001-12-12
申请人： Youfeng Wu , Tin-Fook Ngai
发明人： Youfeng Wu , Tin-Fook Ngai
IPC分类号： G06F9/312
CPC分类号： G06F9/383 , G06F9/3832 , G06F9/3842 , G06F9/3861
摘要： A data processing apparatus, a computer, an article including a machine-accessible medium, and a method of processing data are disclosed. The data processing apparatus may include a pair of pipelines sharing an instruction cache, data cache, and a branch predictor with the second pipeline running ahead of the first pipeline using a data value prediction module. The pipelines may be included in one or more processors and coupled to a memory to form a computer. The method includes executing a plurality of instructions using the pipeline pair, such that when a cache miss is encountered by the second pipeline during execution of a LOAD instruction, the data value prediction module supplies a predicted load value in lieu of a cached value, enabling continued execution of the plurality of instructions by the second pipeline without waiting for the return of the cached value.
摘要翻译：公开了一种数据处理装置，计算机，包括机器可访问介质的物品和处理数据的方法。数据处理装置可以包括使用数据值预测模块，共享指令高速缓存，数据高速缓存和分支预测器的一对管线，其中第二管线在第一管线之前运行。管线可以包括在一个或多个处理器中并且耦合到存储器以形成计算机。该方法包括使用流水线对来执行多个指令，使得当在执行LOAD指令期间由第二流水线遇到高速缓存未命中时，数据值预测模块提供代替缓存值的预测负载值，使能通过第二管道继续执行多个指令，而不等待返回缓存的值。

4. 发明申请

US20140122832A1 PARTIAL VECTORIZATION COMPILATION SYSTEM 有权
标题翻译：部分矢量编译系统
公开(公告)号：US20140122832A1
公开(公告)日：2014-05-01
申请号：US13995721
申请日：2012-10-25
申请人： Tin-Fook Ngai , Chunxiao Lin , Yingzhe Shen , Chao Zhang
发明人： Tin-Fook Ngai , Chunxiao Lin , Yingzhe Shen , Chao Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F8/433 , G06F8/4441 , G06F8/452
摘要： Generally, this disclosure provides technologies for generating and executing partially vectorized code that may include backward dependencies within a loop body of the code to be vectorized. The method may include identifying backward dependencies within a loop body of the code; selecting one or more ranges of iterations within the loop body, wherein the selected ranges exclude the identified backward dependencies; and vectorizing the selected ranges. The system may include a vector processor configured to provide predicated vector instruction execution, loop iteration range enabling, and dynamic loop dependence checking.
摘要翻译：通常，本公开提供了用于生成和执行部分向量化代码的技术，其可以包括要被矢量化的代码的循环体内的后向依赖性。该方法可以包括识别代码的循环体内的后向依赖性; 在所述循环体内选择一个或多个迭代范围，其中所选择的范围排除所识别的后向依赖性; 并对所选范围进行向量化。该系统可以包括被配置为提供预测向量指令执行，循环迭代范围使能和动态循环依赖性检查的向量处理器。

5. 发明申请

US20050182602A1 Computation of all-pairs reaching probabilities in software systems 有权
标题翻译：软件系统中所有对达到概率的计算
公开(公告)号：US20050182602A1
公开(公告)日：2005-08-18
申请号：US10778545
申请日：2004-02-17
申请人： Chu-Cheow Lim , Zhao Du , Tin-Fook Ngai
发明人： Chu-Cheow Lim , Zhao Du , Tin-Fook Ngai
IPC分类号： G06F17/10
CPC分类号： G06F9/44
摘要： A Markov chain model of a software system may be used to compute all-pairs reaching probabilities to provide guidance in performing speculative operations with respect to the software system.
摘要翻译：可以使用软件系统的马可夫链模型来计算所有对达成概率，以提供关于软件系统执行投机操作的指导。

6. 发明申请

US20180225117A1 METHOD AND SYSTEM TO PROVIDE USER-LEVEL MULTITHREADING 审中-公开
公开(公告)号：US20180225117A1
公开(公告)日：2018-08-09
申请号：US15943611
申请日：2018-04-02
申请人： Ed Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
发明人： Ed Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

7. 发明授权

US09703558B2 Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate 有权
公开(公告)号：US09703558B2
公开(公告)日：2017-07-11
申请号：US13991877
申请日：2011-12-23
申请人： Victor W. Lee , Daehyun Kim , Tin-Fook Ngai , Jayashankar Bharadwaj , Albert Hartono , Sara Baghsorkhi , Nalini Vasudevan
发明人： Victor W. Lee , Daehyun Kim , Tin-Fook Ngai , Jayashankar Bharadwaj , Albert Hartono , Sara Baghsorkhi , Nalini Vasudevan
IPC分类号： G06F15/76 , G06F9/305 , G06F9/315 , G06F15/80 , G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30025 , G06F9/30072 , G06F15/8007 , G06F15/8053 , G06F15/8084 , G06F15/8092
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.

8. 发明申请

US20140089634A1 APPARATUS AND METHOD FOR DETECTING IDENTICAL ELEMENTS WITHIN A VECTOR REGISTER 审中-公开
标题翻译：用于检测矢量寄存器中的标识元素的装置和方法
公开(公告)号：US20140089634A1
公开(公告)日：2014-03-27
申请号：US13995490
申请日：2011-12-23
申请人： Victor W. Lee , Daehyun Kim , Tin-Fook Ngai , Jayashankar Bharadwaj , Albert Hartono , Sara S. Baghsorkhi , Nalini Vasudevan
发明人： Victor W. Lee , Daehyun Kim , Tin-Fook Ngai , Jayashankar Bharadwaj , Albert Hartono , Sara S. Baghsorkhi , Nalini Vasudevan
IPC分类号： G06F9/30
CPC分类号： G06F9/30101 , G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/30145
摘要： An apparatus, system and method are described for identifying identical elements in a vector register. For example, a computer implemented method according to one embodiment comprises the operations of: reading each active element from a first vector register, each active element having a defined bit position within the first vector register; reading each element from a second vector register, each element having a defined bit position within the second vector register corresponding to a bit position of a current active element in the first vector register; reading an input mask register, the input mask register identifying active bit positions in the second vector register for which comparisons are to be made with values in the first vector register, the comparison operations comprising: comparing each active element in the second vector register with elements in the first vector register having bit positions preceding the bit position of the current active element in the second vector register; and setting a bit position in an output mask register equal to a true value if all of the preceding bit positions in the first vector register are equal to the bit in the current active bit position in the second vector register.
摘要翻译：描述了用于识别向量寄存器中的相同元件的装置，系统和方法。例如，根据一个实施例的计算机实现的方法包括以下操作：从第一向量寄存器读取每个活动元件，每个有源元件在第一向量寄存器内具有定义的位位置; 从第二向量寄存器读取每个元素，每个元素在第二向量寄存器内具有对应于第一向量寄存器中当前有效元素的位位置的定义的位位置; 读取输入掩码寄存器，所述输入掩码寄存器识别所述第二向量寄存器中的活动位位置，用于与所述第一向量寄存器中的值进行比较，所述比较操作包括：将所述第二向量寄存器中的每个有效元素与元素在第一矢量寄存器中，位于第二向量寄存器中当前有效元件的位位置之前的位位置; 并且如果第一向量寄存器中的所有先前位位置等于第二向量寄存器中的当前活动位位置中的位，则将输出屏蔽寄存器中的位位置设置为等于真值。

9. 发明授权

US08296748B2 Method and system for intermediate representation of source code 有权
标题翻译：源代码的中间表示方法和系统
公开(公告)号：US08296748B2
公开(公告)日：2012-10-23
申请号：US12178842
申请日：2008-07-24
申请人： Buqi Cheng , Tin-Fook Ngai , Zhaohui Du , PeiNan Zhang
发明人： Buqi Cheng , Tin-Fook Ngai , Zhaohui Du , PeiNan Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/433
摘要： A method to provide effective control and data flow information in an Intermediate Representation (IR) form. A Path Sensitive single Assignment (PSA) IR form with effective and explicit control and data path information supports control flow sensitive optimizations such as path sensitive symbolic substitution, array privatization and speculative multi threading. In the definition of PSA form, besides defining new versioned variables, the gamma functions keep control path information. The gamma function in PSA form keeps the basic attribute of SSA IR form and only one definition exists for each use. Therefore, all existing Single Static Assignment (SSA) IR form based analysis can be applied in PSA form. The gamma function in PSA form keeps all essential control flow information and eliminates unnecessary predicates at the same time.
摘要翻译：一种以中间表示（IR）形式提供有效控制和数据流信息的方法。路径敏感单分配（PSA）具有有效和显式控制和数据路径信息的IR形式支持控制流敏感优化，如路径敏感符号替换，数组私有化和投机多线程。在PSA形式的定义中，除了定义新的版本变量之外，伽马函数还保留了控制路径信息。 PSA形式的伽玛函数保持SSA IR形式的基本属性，并且每次使用只存在一个定义。因此，所有现有的单静态分配（SSA）IR形式分析可以以PSA形式应用。 PSA形式的伽玛功能保留所有必要的控制流信息，同时消除不必要的谓词。

10. 发明申请

US20050223199A1 Method and system to provide user-level multithreading 有权
标题翻译：方法和系统提供用户级多线程
公开(公告)号：US20050223199A1
公开(公告)日：2005-10-06
申请号：US10816103
申请日：2004-03-31
申请人： Edward Grochowski , Hong Wang , John Shen , Perry Wang , Jamison Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
发明人： Edward Grochowski , Hong Wang , John Shen , Perry Wang , Jamison Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
IPC分类号： G06F9/30 , G06F9/38 , G06F9/48 , G06F9/44
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
摘要翻译：公开了提供用户级多线程的方法和系统。根据本技术的方法包括接收经由指令集架构（ISA）执行一个或多个共享资源线程（碎片）的编程指令。一个或多个指令指针通过ISA配置; 并且一个或多个碎片与微处理器同时执行，其中微处理器包括多个指令定序器。

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