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1. 发明授权

US07188234B2 Run-ahead program execution with value prediction 失效
标题翻译：带有价值预测的预测程序执行
公开(公告)号：US07188234B2
公开(公告)日：2007-03-06
申请号：US10017793
申请日：2001-12-12
申请人： Youfeng Wu , Tin-Fook Ngai
发明人： Youfeng Wu , Tin-Fook Ngai
IPC分类号： G06F9/312
CPC分类号： G06F9/383 , G06F9/3832 , G06F9/3842 , G06F9/3861
摘要： A data processing apparatus, a computer, an article including a machine-accessible medium, and a method of processing data are disclosed. The data processing apparatus may include a pair of pipelines sharing an instruction cache, data cache, and a branch predictor with the second pipeline running ahead of the first pipeline using a data value prediction module. The pipelines may be included in one or more processors and coupled to a memory to form a computer. The method includes executing a plurality of instructions using the pipeline pair, such that when a cache miss is encountered by the second pipeline during execution of a LOAD instruction, the data value prediction module supplies a predicted load value in lieu of a cached value, enabling continued execution of the plurality of instructions by the second pipeline without waiting for the return of the cached value.
摘要翻译：公开了一种数据处理装置，计算机，包括机器可访问介质的物品和处理数据的方法。数据处理装置可以包括使用数据值预测模块，共享指令高速缓存，数据高速缓存和分支预测器的一对管线，其中第二管线在第一管线之前运行。管线可以包括在一个或多个处理器中并且耦合到存储器以形成计算机。该方法包括使用流水线对来执行多个指令，使得当在执行LOAD指令期间由第二流水线遇到高速缓存未命中时，数据值预测模块提供代替缓存值的预测负载值，使能通过第二管道继续执行多个指令，而不等待返回缓存的值。

2. 发明申请

US20110167416A1 SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTEM TO AUTOMATICALLY DECOMPOSE A PROGRAM TO MULTIPLE PARALLEL THREADS 有权
标题翻译：用于硬件和软件系统的系统，设备和方法，用于自动将程序分解成多个并行线程
公开(公告)号：US20110167416A1
公开(公告)日：2011-07-07
申请号：US12978557
申请日：2010-12-25
申请人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
发明人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
IPC分类号： G06F9/45
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
摘要翻译：描述了用于将程序自动分解为多个并行线程的硬件和软件系统的系统，装置和方法。在一些实施例中，系统和装置执行原始代码分解和/或生成的线程执行的方法。

3. 发明授权

US09672019B2 Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads 有权
公开(公告)号：US09672019B2
公开(公告)日：2017-06-06
申请号：US12978557
申请日：2010-12-25
申请人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
发明人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
IPC分类号： G06F9/45 , G06F9/38 , G06F9/54 , G06F11/36
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

4. 发明申请

US20160188305A1 TECHNOLOGIES FOR LOW-LEVEL COMPOSABLE HIGH PERFORMANCE COMPUTING LIBRARIES 有权
标题翻译：低水平复合高性能计算机图形技术
公开(公告)号：US20160188305A1
公开(公告)日：2016-06-30
申请号：US14583657
申请日：2014-12-27
申请人： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Arthur N. Glew , Paul M. PetersEn , Victor W. Lee , P.G. Lowney , Arch D. Robinson , Cheng Wang
发明人： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Arthur N. Glew , Paul M. PetersEn , Victor W. Lee , P.G. Lowney , Arch D. Robinson , Cheng Wang
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/43 , G06F8/31 , G06F8/443 , G06F8/4441 , G06F8/453 , G06F8/49 , G06F8/54
摘要： Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.
摘要翻译：用于生成可组合库函数的技术包括：第一计算设备，其包括被配置为编译可组合库的库编译器和第二计算设备，所述第二计算设备包括应用编译器，所述应用编译器被配置为基于以不同级别写入的多个抽象来组合所述可组合库的库函数的抽象。例如，抽象可以包括高级别的算法抽象，中等级别的阻塞算法抽象，以及低级别的基于区域的代码抽象。在此描述和要求保护的其它实施例。

5. 发明申请

US20150277968A1 SOFTWARE REPLAYER FOR TRANSACTIONAL MEMORY PROGRAMS 有权
标题翻译：用于实时存储器程序的软件更新程序
公开(公告)号：US20150277968A1
公开(公告)日：2015-10-01
申请号：US14226312
申请日：2014-03-26
申请人： Justin E. Gottschlich , Gilles A. Pokam , Shiliang Hu , Rolf Kassa , Youfeng Wu , Irina Calciu
发明人： Justin E. Gottschlich , Gilles A. Pokam , Shiliang Hu , Rolf Kassa , Youfeng Wu , Irina Calciu
IPC分类号： G06F9/46 , G06F11/36 , G11C7/10
CPC分类号： G06F9/467 , G06F11/34 , G06F11/362 , G06F11/3648
摘要： A system is disclosed that includes a processor and a dynamic random access memory (DRAM). The processor includes a hybrid transactional memory (HyTM) that includes hardware transactional memory (HTM), and a program debugger to replay a program that includes an HTM instruction and that has been executed has been executed using the HyTM. The program debugger includes a software emulator that is to replay the HTM instruction by emulation of the HTM. Other embodiments are disclosed and claimed.
摘要翻译：公开了一种包括处理器和动态随机存取存储器（DRAM）的系统。处理器包括包括硬件事务存储器（HTM）的混合事务处理存储器（HyTM），并且使用HyTM执行用于重放包括HTM指令并已被执行的程序的程序调试器。程序调试器包括一个软件仿真器，通过仿真HTM来重播HTM指令。公开和要求保护其他实施例。

6. 发明申请

US20140208085A1 INSTRUCTION AND LOGIC TO EFFICIENTLY MONITOR LOOP TRIP COUNT 有权
标题翻译：指令和逻辑到有效的监视器循环次数
公开(公告)号：US20140208085A1
公开(公告)日：2014-07-24
申请号：US13996861
申请日：2012-03-30
申请人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
发明人： Jaewoong Chung , Hyunchul Park , Hongbo Rong , Cheng Wang , Youfeng Wu
IPC分类号： G06F9/32
CPC分类号： G06F9/325 , G06F8/443 , G06F9/30072 , G06F9/3842 , G06F9/3857 , G06F11/3409 , G06F11/348 , G06F2201/88
摘要： Logic and instruction to efficiently monitor loop trip count. Loop trip count information of a loop may be stored in a dedicated hardware buffer. Average loop trip count of the loop may be calculated based on the stored loop trip count information. Based on the average trip count, loop optimizations may be applied or removed from the loop. The stored loop trip count information may include an identifier identifying the loop, a total loop trip count of the loop, and an exit count of the loop.
摘要翻译：有效监控回路行程数的逻辑和指令。循环的循环行程计数信息可以存储在专用硬件缓冲器中。可以基于存储的循环行程计数信息来计算循环的平均循环行程计数。基于平均行程计数，循环优化可以从循环中应用或移除。存储的循环行程计数信息可以包括标识循环的标识符，循环的总循环行程计数以及循环的退出计数。

7. 发明申请

US20130346781A1 Power Gating Functional Units Of A Processor 有权
标题翻译：处理器的电源门控功能单元
公开(公告)号：US20130346781A1
公开(公告)日：2013-12-26
申请号：US13528548
申请日：2012-06-20
申请人： Jaewoong Chung , Hanjun Kim , Youfeng Wu
发明人： Jaewoong Chung , Hanjun Kim , Youfeng Wu
IPC分类号： G06F1/32 , G06F9/30 , G06F1/00
CPC分类号： G06F1/3234 , G06F1/3243 , G06F1/3287 , G06F9/30 , G06F9/30083 , G06F9/3836 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： In one embodiment, the present invention includes an apparatus having a core including functional units each to execute instructions of a target instruction set architecture (ISA) and a power controller to control a power mode of a first functional unit responsive to a power identification field of a power instruction of a power region of a code block to be executed on the core. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种具有核心的装置，其核心包括各自执行目标指令集架构（ISA）的指令的功能单元和功率控制器，以响应于功率识别领域来控制第一功能单元的功率模式要在核心上执行的代码块的功率区域的功率指令。描述和要求保护其他实施例。

8. 发明授权

US08443343B2 Context-sensitive slicing for dynamically parallelizing binary programs 有权
标题翻译：用于动态并行化二进制程序的上下文相关切片
公开(公告)号：US08443343B2
公开(公告)日：2013-05-14
申请号：US12607589
申请日：2009-10-28
申请人： Joseph Blomstedt , Cheng Wang , Youfeng Wu
发明人： Joseph Blomstedt , Cheng Wang , Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F11/3604 , G06F8/433 , G06F8/456
摘要： In one embodiment of the invention a method comprising (1) receiving an unstructured binary code region that is single-threaded; (2) determining a slice criterion for the region; (3) determining a call edge, a return edge, and a fallthrough pseudo-edge for the region based on analysis of the region at a binary level; and (4) determining a context-sensitive slice based on the call edge, the return edge, the fallthrough pseudo-edge, and the slice criterion. Embodiments of the invention may include a program analysis technique that can be used to provide context-sensitive slicing of binary programs for slicing hot regions identified at runtime, with few underlying assumptions about the program from which the binary is derived. Also, in an embodiment a slicing method may include determining a context-insensitive slice, when a time limit is met, by determining the context-insensitive slice while treating call edges as a normal control flow edges.
摘要翻译：在本发明的一个实施例中，一种方法包括（1）接收单线程的非结构化二进制码区域; （2）确定该区域的切片标准; （3）基于二进制级别的区域的分析确定该区域的通话边缘，返回边缘和下降伪边缘; 和（4）基于呼叫边缘，返回边缘，下降伪边缘和切片标准来确定上下文敏感切片。本发明的实施例可以包括程序分析技术，其可以用于提供二进制程序的上下文敏感切片，用于对在运行时识别的热区域进行切片，而关于从其导出二进制的程序的几个基本假设。此外，在一个实施例中，切片方法可以包括当满足时间限制时，通过在将呼叫边缘视为正常控制流边缘的同时确定上下文不敏感切片来确定上下文不敏感切片。

9. 发明授权

US08321840B2 Software flow tracking using multiple threads 有权
标题翻译：使用多线程的软件流跟踪
公开(公告)号：US08321840B2
公开(公告)日：2012-11-27
申请号：US11965271
申请日：2007-12-27
申请人： Vijayanand Nagarajan , Ho-Seop Kim , Youfeng Wu , Rajiv Gupta
发明人： Vijayanand Nagarajan , Ho-Seop Kim , Youfeng Wu , Rajiv Gupta
IPC分类号： G06F9/44
CPC分类号： G06F21/566 , G06F8/33 , G06F11/3636
摘要： Methods, systems and machine readable media are disclosed for performing dynamic information flow tracking. One method includes executing operations of a program with a main thread, and tracking the main thread's execution of the operations of the program with a tracking thread. The method further includes updating, with the tracking thread, a taint value associated with the value of the main thread to reflect whether the value is tainted, and determining, with the tracking thread based upon the taint value, whether use of the value by the main thread violates a specific security policy.
摘要翻译：公开了用于执行动态信息流跟踪的方法，系统和机器可读介质。一种方法包括执行具有主线程的程序的操作，并且使用跟踪线程跟踪主线程对程序的操作的执行。该方法还包括利用跟踪线程来更新与主线程的值相关联的污点值，以反映该值是否被污染，并且基于该着色值确定跟踪线程是否使用该值主线程违反了特定的安全策略。

10. 发明申请

US20120198426A1 METHODS AND APPARATUS TO FORM A RESILIENT OBJECTIVE INSTRUCTION CONSTRUCT 有权
标题翻译：形成适应性目标指导建议的方法和设备
公开(公告)号：US20120198426A1
公开(公告)日：2012-08-02
申请号：US13442703
申请日：2012-04-09
申请人： Youfeng Wu , Cheng Wang , Ho-Seop Kim
发明人： Youfeng Wu , Cheng Wang , Ho-Seop Kim
IPC分类号： G06F9/45
CPC分类号： G06F11/28 , G06F8/52 , G06F9/30087 , G06F9/45516
摘要： Methods and an apparatus to form a resilient objective instruction construct are provided. An example method obtains a source instruction construct and forms a resilient objective instruction construct by compiling one or more resilient transactions.
摘要翻译：提供了形成弹性目标指令结构的方法和装置。示例性方法通过编译一个或多个弹性事务来获得源指令结构并形成弹性目标指令结构。

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