专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20150095674A1 Utilization of Processor Capacity at Low Operating Frequencies 有权
标题翻译：处理器容量在低工作频率下的利用率
公开(公告)号：US20150095674A1
公开(公告)日：2015-04-02
申请号：US14039368
申请日：2013-09-27
申请人： Ruchira Sasanka , Alexander Gendler , Udi Sherel
发明人： Ruchira Sasanka , Alexander Gendler , Udi Sherel
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/266 , G06F1/324 , G06F12/0223 , G06F12/084 , G06F2212/62 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括一个或多个核，包括可在最小工作电压和最大工作电压之间的工作电压下工作的第一核。处理器还包括功率控制单元，其包括第一逻辑，以便响应于小于或等于阈值电压的工作电压来使辅助逻辑耦合到第一核心，并且禁用辅助逻辑与第一核心的耦合响应使工作电压大于阈值电压。描述和要求保护其他实施例。

2. 发明申请

US20140181487A1 METHOD, APPARATUS, SYSTEM FOR CONTINUOUS AUTOMATIC TUNING OF CODE REGIONS 有权
标题翻译：方法，装置，代码区域连续自动调谐系统
公开(公告)号：US20140181487A1
公开(公告)日：2014-06-26
申请号：US13722243
申请日：2012-12-20
申请人： Ruchira Sasanka
发明人： Ruchira Sasanka
IPC分类号： G06F9/44
CPC分类号： G06F9/4401 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/4411 , G06F11/3409 , G06F11/3442 , G06F11/3452 , G06F11/3466 , G06F12/023 , G06F12/0638 , G06F15/781 , G06F2201/865 , G06F2201/88 , G06F2201/885 , G06F2212/205 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： Described herein are mechanisms for continuous automatic tuning of code regions for optimal hardware configurations for the code regions. One mechanism automatically tunes the tunable parameters for a demarcated code region by calculating metrics while executing the code region with different sets of tunable parameters and selecting one of the different sets based on the calculated metrics.
摘要翻译：这里描述了用于代码区域的最佳硬件配置的连续自动调整代码区域的机制。一种机制通过在使用不同的可调参数集合执行代码区域的同时计算度量值来自动调整分割代码区域的可调参数，并根据计算的指标选择不同集合之一。

3. 发明授权

US09672019B2 Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads 有权
公开(公告)号：US09672019B2
公开(公告)日：2017-06-06
申请号：US12978557
申请日：2010-12-25
申请人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
发明人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
IPC分类号： G06F9/45 , G06F9/38 , G06F9/54 , G06F11/36
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

4. 发明授权

US09323528B2 Method, apparatus, system creating, executing and terminating mini-threads 有权
标题翻译：方法，设备，系统创建，执行和终止微型线程
公开(公告)号：US09323528B2
公开(公告)日：2016-04-26
申请号：US13722588
申请日：2012-12-20
申请人： Ruchira Sasanka
发明人： Ruchira Sasanka
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3009 , G06F9/30098 , G06F9/30189 , G06F9/3851 , G06F9/3877
摘要： Described herein are mechanisms for creating, executing, and terminating mini-threads. A processor executes instructions with a primary thread in a first execution mode, and to execute an instruction to create a secondary mini-thread that is associated with a first subset of registers and associates the primary thread with a second subset of the registers during a second execution mode. During the second execution mode, the primary thread operates as a primary mini-thread.
摘要翻译：这里描述了用于创建，执行和终止微型线程的机制。处理器以第一执行模式执行具有主线程的指令，并且执行指令以创建与第一寄存器子集相关联的辅助微线程，并且在第二执行模式期间将主线程与寄存器的第二子集相关联执行模式。在第二执行模式期间，主线程作为主要的微型线程运行。

5. 发明申请

US20180189040A1 AUTOMATIC IDENTIFICATION AND GENERATION OF NON-TEMPORAL STORE AND LOAD OPERATIONS IN A DYNAMIC OPTIMIZATION ENVIRONMENT 审中-公开
公开(公告)号：US20180189040A1
公开(公告)日：2018-07-05
申请号：US15393931
申请日：2016-12-29
申请人： Ruchira Sasanka
发明人： Ruchira Sasanka
IPC分类号： G06F9/45 , G06F9/455
CPC分类号： G06F8/4442 , G06F9/30043 , G06F9/45516 , G06F11/34
摘要： Techniques are disclosed to identify a frequently-executed region of code during runtime execution of the code, generate initial profiling code for the frequently-executed region of code, cause the initial profiling code to be executed for a minimum number of processing cycles of the computer, and identify replacement candidate store instruction(s) that store a value that is not read by the frequently-executed region of code during execution of the initial profiling code. Replacement candidate load instruction(s) may also be identified that load a value that is not stored or loaded by the frequently-executed region of code during execution of the initial profiling code. Optimized code for the frequently-executed region of code may be generated by replacing each of the replacement candidate store or load instructions(s) with a non-temporal store or load instruction. The optimized code may be executed instead of the frequently-executed region of code during subsequent runtime execution.

6. 发明授权

US09189233B2 Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads 有权
标题翻译：用于硬件和软件系统的系统，设备和方法，以将程序自动分解为多个并行线程
公开(公告)号：US09189233B2
公开(公告)日：2015-11-17
申请号：US13533821
申请日：2012-06-26
申请人： Ruchira Sasanka , Abhinav Das , Jeffrey J. Cook , Jayaram Bobba , Arvind Krishnaswamy , David J. Sager , Suresh Srinivas
发明人： Ruchira Sasanka , Abhinav Das , Jeffrey J. Cook , Jayaram Bobba , Arvind Krishnaswamy , David J. Sager , Suresh Srinivas
IPC分类号： G06F9/00 , G06F9/30 , G06F11/36 , G06F9/38 , G06F9/54 , G06F9/45
CPC分类号： G06F11/3612 , G06F8/456 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. For example, a method according to one embodiment comprises: analyzing a single-threaded region of executing program code, the analysis including identifying dependencies within the single-threaded region; determining portions of the single-threaded region of executing program code which may be executed in parallel based on the analysis; assigning the portions to two or more parallel execution tracks; and executing the portions in parallel across the assigned execution tracks.
摘要翻译：描述了用于将程序自动分解为多个并行线程的硬件和软件系统的系统，装置和方法。例如，根据一个实施例的方法包括：分析执行程序代码的单线程区域，所述分析包括识别所述单线程区域内的依赖性; 确定可以基于分析并行执行执行程序代码的单线程区域的部分; 将所述部分分配给两个或更多个并行执行轨道; 并且在分配的执行轨道上并行地执行这些部分。

7. 发明申请

US20140258677A1 ANALYZING POTENTIAL BENEFITS OF VECTORIZATION 有权
标题翻译：分析潜在收益的潜在优势
公开(公告)号：US20140258677A1
公开(公告)日：2014-09-11
申请号：US13997140
申请日：2013-03-05
申请人： Ruchira Sasanka , Jeffrey J. Cook , Abhinav Das , Jayaram Bobba , Michael R. Greenfield , Suresh Srinivas
发明人： Ruchira Sasanka , Jeffrey J. Cook , Abhinav Das , Jayaram Bobba , Michael R. Greenfield , Suresh Srinivas
IPC分类号： G06F9/30
CPC分类号： G06F8/41 , G06F8/456
摘要： Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media (transitory and non-transitory) are described herein for analyzing execution of a plurality of executable instructions and, based on the analysis, providing an indication of a benefit to be obtained by vectorization of at least a subset of the plurality of executable instructions. In various embodiments, the analysis may include identification of the subset of the plurality of executable instructions suitable for conversion to one or more single-instruction multiple-data (“SIMD”) instructions.
摘要翻译：本文描述了计算机实现的方法，系统，计算设备和计算机可读介质（暂时性和非暂时性）的实施例，用于分析多个可执行指令的执行，并且基于该分析，提供对可以通过对多个可执行指令的至少一个子集进行向量化来获得。在各种实施例中，分析可以包括识别适合于转换成一个或多个单指令多数据（“SIMD”）指令的多个可执行指令的子集。

8. 发明申请

US20130283022A1 SYSTEM, APPARATUS AND METHOD FOR TRANSLATING VECTOR INSTRUCTIONS 有权
标题翻译：用于转换矢量指令的系统，装置和方法
公开(公告)号：US20130283022A1
公开(公告)日：2013-10-24
申请号：US13993603
申请日：2011-12-06
申请人： Ruchira Sasanka
发明人： Ruchira Sasanka
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/3001 , G06F9/30018 , G06F9/30036 , G06F9/30076 , G06F9/3017 , G06F9/30174
摘要： Vector translation instructions are used to demarcate the beginning and the end of a code region to be translated. The code region includes a first set of vector instructions defined in an instruction set of a source processor. A processor receives the vector translation instructions and the demarcated code region, and translates the code region into translated code. The translated code includes a second set of vector instructions defined in an instruction set of a target processor. The translated code is executed by the target processor to produce a result value, the result value being the same as an original result value produced by the source processor executing the code region. The target processor stores the result value at a location that is not a vector register, the location being the same as an original location used by the source processor to store the original result value.
摘要翻译：矢量翻译指令用于划分要翻译的代码区域的开始和结束。代码区域包括在源处理器的指令集中定义的第一组向量指令。处理器接收向量转换指令和划分的代码区域，并将代码区域转换为翻译代码。翻译的代码包括在目标处理器的指令集中定义的第二组矢量指令。翻译后的代码由目标处理器执行以产生结果值，结果值与由执行代码区域的源处理器产生的原始结果值相同。目标处理器将结果值存储在不是向量寄存器的位置处，该位置与源处理器用于存储原始结果值的原始位置相同。

9. 发明授权

US09424042B2 System, apparatus and method for translating vector instructions 有权
标题翻译：用于翻译矢量指令的系统，装置和方法
公开(公告)号：US09424042B2
公开(公告)日：2016-08-23
申请号：US13993603
申请日：2011-12-06
申请人： Ruchira Sasanka
发明人： Ruchira Sasanka
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/3001 , G06F9/30018 , G06F9/30036 , G06F9/30076 , G06F9/3017 , G06F9/30174
摘要： Vector translation instructions are used to demarcate the beginning and the end of a code region to be translated. The code region includes a first set of vector instructions defined in an instruction set of a source processor. A processor receives the vector translation instructions and the demarcated code region, and translates the code region into translated code. The translated code includes a second set of vector instructions defined in an instruction set of a target processor. The translated code is executed by the target processor to produce a result value, the result value being the same as an original result value produced by the source processor executing the code region. The target processor stores the result value at a location that is not a vector register, the location being the same as an original location used by the source processor to store the original result value.
摘要翻译：矢量翻译指令用于划分要翻译的代码区域的开始和结束。代码区域包括在源处理器的指令集中定义的第一组向量指令。处理器接收向量转换指令和划分的代码区域，并将代码区域转换为翻译代码。翻译的代码包括在目标处理器的指令集中定义的第二组矢量指令。翻译后的代码由目标处理器执行以产生结果值，结果值与由执行代码区域的源处理器产生的原始结果值相同。目标处理器将结果值存储在不是向量寄存器的位置处，该位置与源处理器用于存储原始结果值的原始位置相同。

10. 发明申请

US20140281424A1 TRACKING CONTROL FLOW OF INSTRUCTIONS 有权
标题翻译：跟踪指令的控制流程
公开(公告)号：US20140281424A1
公开(公告)日：2014-09-18
申请号：US13834049
申请日：2013-03-15
申请人： Jayaram Bobba , Ruchira Sasanka , Jeffrey J. Cook , Abhinav Das , Arvind Krishnaswamy , David J. Sager , Jason M. Agron
发明人： Jayaram Bobba , Ruchira Sasanka , Jeffrey J. Cook , Abhinav Das , Arvind Krishnaswamy , David J. Sager , Jason M. Agron
IPC分类号： G06F9/30
CPC分类号： G06F9/3005 , G06F8/433 , G06F11/0715 , G06F11/0721 , G06F11/076 , G06F11/3466
摘要： A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.
摘要翻译：公开了一种用于跟踪应用程序中的指令的控制流程并基于应用程序中的指令的控制流程执行处理设备的一个或多个优化的机制。生成控制流数据以指示应用程序中的指令块的控制流程。控制流数据可以包括指示是否可以针对不同的指令块执行优化的注释。控制流数据还可以用于跟踪指令的执行以确定指令块中的指令是否被分配给处理器的线程，进程和/或执行核心，并且确定错误是否具有在执行指令期间发生。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式