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1. 发明申请

US20180225117A1 METHOD AND SYSTEM TO PROVIDE USER-LEVEL MULTITHREADING 审中-公开
公开(公告)号：US20180225117A1
公开(公告)日：2018-08-09
申请号：US15943611
申请日：2018-04-02
申请人： Ed Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
发明人： Ed Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

2. 发明申请

US20180225118A1 METHOD AND SYSTEM TO PROVIDE USER-LEVEL MULTITHREADING 审中-公开
公开(公告)号：US20180225118A1
公开(公告)日：2018-08-09
申请号：US15943614
申请日：2018-04-02
申请人： Ed Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
发明人： Ed Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

3. 发明申请

US20130111194A1 METHOD AND SYSTEM TO PROVIDE USER-LEVEL MULTITHREADING 审中-公开
标题翻译：提供用户级多媒体的方法和系统
公开(公告)号：US20130111194A1
公开(公告)日：2013-05-02
申请号：US13722481
申请日：2012-12-20
申请人： Ed Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Colins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
发明人： Ed Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Colins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
IPC分类号： G06F9/30
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
摘要翻译：公开了提供用户级多线程的方法和系统。根据本技术的方法包括接收经由指令集架构（ISA）执行一个或多个共享资源线程（碎片）的编程指令。一个或多个指令指针通过ISA配置; 并且一个或多个碎片与微处理器同时执行，其中微处理器包括多个指令定序器。

4. 发明授权

US09189230B2 Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution 有权
标题翻译：方法和系统提供并发用户级，非特权共享资源线程的创建和执行
公开(公告)号：US09189230B2
公开(公告)日：2015-11-17
申请号：US10816103
申请日：2004-03-31
申请人： Edward T. Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James P. Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
发明人： Edward T. Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James P. Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
摘要翻译：公开了提供用户级多线程的方法和系统。根据本技术的方法包括接收经由指令集架构（ISA）执行一个或多个共享资源线程（碎片）的编程指令。一个或多个指令指针通过ISA配置; 并且一个或多个碎片与微处理器同时执行，其中微处理器包括多个指令定序器。

5. 发明申请

US20050223199A1 Method and system to provide user-level multithreading 有权
标题翻译：方法和系统提供用户级多线程
公开(公告)号：US20050223199A1
公开(公告)日：2005-10-06
申请号：US10816103
申请日：2004-03-31
申请人： Edward Grochowski , Hong Wang , John Shen , Perry Wang , Jamison Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
发明人： Edward Grochowski , Hong Wang , John Shen , Perry Wang , Jamison Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
IPC分类号： G06F9/30 , G06F9/38 , G06F9/48 , G06F9/44
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
摘要翻译：公开了提供用户级多线程的方法和系统。根据本技术的方法包括接收经由指令集架构（ISA）执行一个或多个共享资源线程（碎片）的编程指令。一个或多个指令指针通过ISA配置; 并且一个或多个碎片与微处理器同时执行，其中微处理器包括多个指令定序器。

6. 发明申请

US20140122832A1 PARTIAL VECTORIZATION COMPILATION SYSTEM 有权
标题翻译：部分矢量编译系统
公开(公告)号：US20140122832A1
公开(公告)日：2014-05-01
申请号：US13995721
申请日：2012-10-25
申请人： Tin-Fook Ngai , Chunxiao Lin , Yingzhe Shen , Chao Zhang
发明人： Tin-Fook Ngai , Chunxiao Lin , Yingzhe Shen , Chao Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F8/433 , G06F8/4441 , G06F8/452
摘要： Generally, this disclosure provides technologies for generating and executing partially vectorized code that may include backward dependencies within a loop body of the code to be vectorized. The method may include identifying backward dependencies within a loop body of the code; selecting one or more ranges of iterations within the loop body, wherein the selected ranges exclude the identified backward dependencies; and vectorizing the selected ranges. The system may include a vector processor configured to provide predicated vector instruction execution, loop iteration range enabling, and dynamic loop dependence checking.
摘要翻译：通常，本公开提供了用于生成和执行部分向量化代码的技术，其可以包括要被矢量化的代码的循环体内的后向依赖性。该方法可以包括识别代码的循环体内的后向依赖性; 在所述循环体内选择一个或多个迭代范围，其中所选择的范围排除所识别的后向依赖性; 并对所选范围进行向量化。该系统可以包括被配置为提供预测向量指令执行，循环迭代范围使能和动态循环依赖性检查的向量处理器。

7. 发明申请

US20050182602A1 Computation of all-pairs reaching probabilities in software systems 有权
标题翻译：软件系统中所有对达到概率的计算
公开(公告)号：US20050182602A1
公开(公告)日：2005-08-18
申请号：US10778545
申请日：2004-02-17
申请人： Chu-Cheow Lim , Zhao Du , Tin-Fook Ngai
发明人： Chu-Cheow Lim , Zhao Du , Tin-Fook Ngai
IPC分类号： G06F17/10
CPC分类号： G06F9/44
摘要： A Markov chain model of a software system may be used to compute all-pairs reaching probabilities to provide guidance in performing speculative operations with respect to the software system.
摘要翻译：可以使用软件系统的马可夫链模型来计算所有对达成概率，以提供关于软件系统执行投机操作的指导。

8. 发明授权

US09703558B2 Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate 有权
公开(公告)号：US09703558B2
公开(公告)日：2017-07-11
申请号：US13991877
申请日：2011-12-23
申请人： Victor W. Lee , Daehyun Kim , Tin-Fook Ngai , Jayashankar Bharadwaj , Albert Hartono , Sara Baghsorkhi , Nalini Vasudevan
发明人： Victor W. Lee , Daehyun Kim , Tin-Fook Ngai , Jayashankar Bharadwaj , Albert Hartono , Sara Baghsorkhi , Nalini Vasudevan
IPC分类号： G06F15/76 , G06F9/305 , G06F9/315 , G06F15/80 , G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30025 , G06F9/30072 , G06F15/8007 , G06F15/8053 , G06F15/8084 , G06F15/8092
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.

9. 发明授权

US09672019B2 Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads 有权
公开(公告)号：US09672019B2
公开(公告)日：2017-06-06
申请号：US12978557
申请日：2010-12-25
申请人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
发明人： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffery J. Cook , Omar M. Shaikh , Suresh Srinivas
IPC分类号： G06F9/45 , G06F9/38 , G06F9/54 , G06F11/36
CPC分类号： G06F8/4442 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/54 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2213/0038
摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

10. 发明申请

US20140089634A1 APPARATUS AND METHOD FOR DETECTING IDENTICAL ELEMENTS WITHIN A VECTOR REGISTER 审中-公开
标题翻译：用于检测矢量寄存器中的标识元素的装置和方法
公开(公告)号：US20140089634A1
公开(公告)日：2014-03-27
申请号：US13995490
申请日：2011-12-23
申请人： Victor W. Lee , Daehyun Kim , Tin-Fook Ngai , Jayashankar Bharadwaj , Albert Hartono , Sara S. Baghsorkhi , Nalini Vasudevan
发明人： Victor W. Lee , Daehyun Kim , Tin-Fook Ngai , Jayashankar Bharadwaj , Albert Hartono , Sara S. Baghsorkhi , Nalini Vasudevan
IPC分类号： G06F9/30
CPC分类号： G06F9/30101 , G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/30145
摘要： An apparatus, system and method are described for identifying identical elements in a vector register. For example, a computer implemented method according to one embodiment comprises the operations of: reading each active element from a first vector register, each active element having a defined bit position within the first vector register; reading each element from a second vector register, each element having a defined bit position within the second vector register corresponding to a bit position of a current active element in the first vector register; reading an input mask register, the input mask register identifying active bit positions in the second vector register for which comparisons are to be made with values in the first vector register, the comparison operations comprising: comparing each active element in the second vector register with elements in the first vector register having bit positions preceding the bit position of the current active element in the second vector register; and setting a bit position in an output mask register equal to a true value if all of the preceding bit positions in the first vector register are equal to the bit in the current active bit position in the second vector register.
摘要翻译：描述了用于识别向量寄存器中的相同元件的装置，系统和方法。例如，根据一个实施例的计算机实现的方法包括以下操作：从第一向量寄存器读取每个活动元件，每个有源元件在第一向量寄存器内具有定义的位位置; 从第二向量寄存器读取每个元素，每个元素在第二向量寄存器内具有对应于第一向量寄存器中当前有效元素的位位置的定义的位位置; 读取输入掩码寄存器，所述输入掩码寄存器识别所述第二向量寄存器中的活动位位置，用于与所述第一向量寄存器中的值进行比较，所述比较操作包括：将所述第二向量寄存器中的每个有效元素与元素在第一矢量寄存器中，位于第二向量寄存器中当前有效元件的位位置之前的位位置; 并且如果第一向量寄存器中的所有先前位位置等于第二向量寄存器中的当前活动位位置中的位，则将输出屏蔽寄存器中的位位置设置为等于真值。

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