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1. 发明授权

US08531046B2 Semiconductor substrates comprising through substrate interconnects that are visible on the substrate backside 有权
标题翻译：包括在衬底背面可见的通过衬底互连的半导体衬底
公开(公告)号：US08531046B2
公开(公告)日：2013-09-10
申请号：US13099672
申请日：2011-05-03
申请人： Dave Pratt , Kyle K. Kirby , Steve Oliver , Mark Hiatt
发明人： Dave Pratt , Kyle K. Kirby , Steve Oliver , Mark Hiatt
IPC分类号： H01L23/544
CPC分类号： H01L21/682 , H01L21/67259 , H01L21/76898 , H01L23/544 , H01L2223/5442 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated.
摘要翻译：本发明包括确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件。在一个实现中，确定包括集成电路的半导体衬底的x-y空间取向的方法包括提供包括至少一个集成电路管芯的半导体衬底。半导体衬底包括电路侧，背面以及从电路侧延伸到背面的多个导电通路。检查半导体衬底背面上的多个导电通孔以确定半导体衬底背面上的多个导电通孔中的至少两个的部分的位置。从确定的位置确定半导体衬底的x-y空间取向。考虑了其他方面和实现。

2. 发明授权

US08294273B2 Methods for fabricating and filling conductive vias and conductive vias so formed 有权
标题翻译：制造和填充如此形成的导电通孔和导电通孔的方法
公开(公告)号：US08294273B2
公开(公告)日：2012-10-23
申请号：US12985570
申请日：2011-01-06
申请人： Salman Akram , William Mark Hiatt , Steve Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
发明人： Salman Akram , William Mark Hiatt , Steve Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/17181 , H01L2924/09701
摘要： Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.
摘要翻译：用于形成导电通孔的方法包括在衬底中形成一个或多个通孔。通孔可以形成有单个掩模，其中在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其它特征用作硬掩模。通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。可以在每个通孔的表面上形成阻挡层。可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

3. 发明申请

US20110095429A1 METHODS FOR FABRICATING AND FILLING CONDUCTIVE VIAS AND CONDUCTIVE VIAS SO FORMED 有权
标题翻译：制造和填充导电VIAS和导电VIAS的方法
公开(公告)号：US20110095429A1
公开(公告)日：2011-04-28
申请号：US12985570
申请日：2011-01-06
申请人： Salman Akram , William Mark Hiatt , Steve Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
发明人： Salman Akram , William Mark Hiatt , Steve Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
IPC分类号： H01L23/48 , H01L23/532
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/17181 , H01L2924/09701
摘要： Methods for forming conductive vias include foiling one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof A barrier layer may be fowled over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.
摘要翻译：用于形成导电通孔的方法包括在基板中形成一个或多个通孔。通孔可以形成有单个掩模，其中在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其它特征用作硬掩模。通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。阻挡层可以在每个通孔的表面上被覆盖。可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

4. 发明授权

US07892972B2 Methods for fabricating and filling conductive vias and conductive vias so formed 有权
标题翻译：制造和填充如此形成的导电通孔和导电通孔的方法
公开(公告)号：US07892972B2
公开(公告)日：2011-02-22
申请号：US11347153
申请日：2006-02-03
申请人： Salman Akram , William Mark Hiatt , Steve Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
发明人： Salman Akram , William Mark Hiatt , Steve Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/17181 , H01L2924/09701
摘要： Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.
摘要翻译：用于形成导电通孔的方法包括在衬底中形成一个或多个通孔。通孔可以形成有单个掩模，其中在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其它特征用作硬掩模。通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。可以在每个通孔的表面上形成阻挡层。可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

5. 发明授权

US07955946B2 Methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices 有权
标题翻译：确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件
公开(公告)号：US07955946B2
公开(公告)日：2011-06-07
申请号：US11439078
申请日：2006-05-22
申请人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
发明人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
IPC分类号： H01L21/76
CPC分类号： H01L21/682 , H01L21/67259 , H01L21/76898 , H01L23/544 , H01L2223/5442 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated.
摘要翻译：本发明包括确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法和半导体器件。在一个实现中，确定包括集成电路的半导体衬底的x-y空间取向的方法包括提供包括至少一个集成电路管芯的半导体衬底。半导体衬底包括电路侧，背面以及从电路侧延伸到背面的多个导电通路。检查半导体衬底背面上的多个导电通孔以确定半导体衬底背面上的多个导电通孔中的至少两个的部分的位置。从确定的位置确定半导体衬底的x-y空间取向。考虑了其他方面和实现。

6. 发明申请

US20070269994A1 Methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices 有权
标题翻译：确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件
公开(公告)号：US20070269994A1
公开(公告)日：2007-11-22
申请号：US11439078
申请日：2006-05-22
申请人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
发明人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
IPC分类号： H01L21/00
CPC分类号： H01L21/682 , H01L21/67259 , H01L21/76898 , H01L23/544 , H01L2223/5442 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated.
摘要翻译：本发明包括确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件。在一个实现中，确定包括集成电路的半导体衬底的x-y空间取向的方法包括提供包括至少一个集成电路管芯的半导体衬底。半导体衬底包括电路侧，背面以及从电路侧延伸到背面的多个导电通路。检查半导体衬底背面上的多个导电通孔以确定半导体衬底背面上的多个导电通孔中的至少两个的部分的位置。从确定的位置确定半导体衬底的x-y空间取向。考虑了其他方面和实现。

7. 发明申请

US20110204526A1 Methods of Determining X-Y Spatial Orientation of a Semiconductor Substrate Comprising an Integrated Circuit, Methods of Positioning a Semiconductor Substrate Comprising an Integrated Circuit, Methods of Processing a Semiconductor Substrate, and Semiconductor Devices 有权
标题翻译：确定包含集成电路的半导体衬底的X-Y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法和半导体器件
公开(公告)号：US20110204526A1
公开(公告)日：2011-08-25
申请号：US13099672
申请日：2011-05-03
申请人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
发明人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
IPC分类号： H01L23/48
CPC分类号： H01L21/682 , H01L21/67259 , H01L21/76898 , H01L23/544 , H01L2223/5442 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated.
摘要翻译：本发明包括确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件。在一个实现中，确定包括集成电路的半导体衬底的x-y空间取向的方法包括提供包括至少一个集成电路管芯的半导体衬底。半导体衬底包括电路侧，背面以及从电路侧延伸到背面的多个导电通路。检查半导体衬底背面上的多个导电通孔以确定半导体衬底背面上的多个导电通孔中的至少两个的部分的位置。从确定的位置确定半导体衬底的x-y空间取向。考虑了其他方面和实现。

8. 发明授权

US08017982B2 Imagers with contact plugs extending through the substrates thereof and imager fabrication methods 有权
标题翻译：具有延伸穿过基板的接触插塞和成像器制造方法的成像器
公开(公告)号：US08017982B2
公开(公告)日：2011-09-13
申请号：US11761904
申请日：2007-06-12
申请人： Kyle K. Kirby , Steve Oliver
发明人： Kyle K. Kirby , Steve Oliver
IPC分类号： H01L31/062
CPC分类号： H01L27/14636 , H01L21/76898 , H01L27/14612 , H01L27/14625 , H01L27/14632 , H01L27/14643
摘要： Methods for fabricating photoimagers, such as complementary metal-oxide-semiconductor (CMOS) imagers, include fabricating image sensing elements, transistors, and other low-elevation features on an active surface of a fabrication substrate, and fabricating contact plugs, conductive lines, external contacts, and other higher-elevation features on the back side of the fabrication substrate. Imagers with image sensing elements and transistors on the active surface and contact plugs that extend through the substrate are also disclosed, as are electronic devices including such imagers.
摘要翻译：用于制造诸如互补金属氧化物半导体（CMOS）成像器的光电效应器的方法包括在制造衬底的有源表面上制造图像感测元件，晶体管和其它低仰角特征，以及制造接触插头，导线，外部接触和其他较高高度的特征。还公开了在活性表面上具有图像感测元件和晶体管的成像器以及延伸穿过衬底的接触插塞，以及包括这种成像器的电子设备也是公开的。

9. 发明申请

US20080290435A1 WAFER LEVEL LENS ARRAYS FOR IMAGE SENSOR PACKAGES AND THE LIKE, IMAGE SENSOR PACKAGES, AND RELATED METHODS 审中-公开
标题翻译：图像传感器包装的像素水平镜头阵列和类似的图像传感器包以及相关方法
公开(公告)号：US20080290435A1
公开(公告)日：2008-11-27
申请号：US11751206
申请日：2007-05-21
申请人： Steve Oliver , Kyle K. Kirby , Warren M. Farnworth , William M. Hiatt , Salman Akram
发明人： Steve Oliver , Kyle K. Kirby , Warren M. Farnworth , William M. Hiatt , Salman Akram
IPC分类号： H01L31/0232 , B29D11/00 , H01L21/00
CPC分类号： B29D11/00375 , H01L27/14618 , H01L27/14625 , H01L27/14632 , H01L27/14685 , H01L2924/0002 , H01L2924/00
摘要： Image sensor packages, lenses therefore, and methods for fabrication are disclosed. A substrate having through-hole vias may be provided, and an array of lenses may be formed in the vias. The lenses may be formed by molding or by tenting material over the vias. An array of lenses may provide a color filter array (CFA). Filters of the CFA may be formed in the vias, and lenses may be formed in or over the vias on either side of the filters. A substrate may include an array of microlenses, and each microlens of the array may correspond to a pixel of an associated image sensor. In other embodiments, each lens of the array may correspond to an imager array of an image sensor. A wafer having an array of lenses may be aligned with and attached to an imager wafer comprising a plurality of image sensor dice, then singulated to form a plurality of image sensor packages.
摘要翻译：公开了图像传感器封装，透镜以及制造方法。可以提供具有通孔过孔的衬底，并且可以在通孔中形成透镜阵列。透镜可以通过模制或通过在通孔上的材料的凸起来形成。透镜阵列可以提供滤色器阵列（CFA）。可以在过孔中形成CFA的过滤器，并且透镜可以形成在过滤器两侧的通孔中或上方。衬底可以包括微透镜阵列，并且阵列的每个微透镜可以对应于相关联的图像传感器的像素。在其他实施例中，阵列的每个透镜可以对应于图像传感器的成像器阵列。具有透镜阵列的晶片可以与包括多个图像传感器芯片的成像器晶片对准并且附接到成像器晶片，然后被单个化以形成多个图像传感器封装。

10. 发明申请

US20110287572A1 SEMICONDUCTOR DEVICE FABRICATION METHODS 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20110287572A1
公开(公告)日：2011-11-24
申请号：US13198533
申请日：2011-08-04
申请人： Kyle K. Kirby , Steve Oliver
发明人： Kyle K. Kirby , Steve Oliver
IPC分类号： H01L31/18 , H01L21/02
CPC分类号： H01L27/14636 , H01L21/76898 , H01L27/14612 , H01L27/14625 , H01L27/14632 , H01L27/14643
摘要： Methods for fabricating semiconductor devices, such as complementary metal-oxide-semiconductor (CMOS) imagers, include fabricating transistors and other low-elevation features on an active surface of a fabrication substrate, and fabricating contact plugs, conductive lines, external contacts, and other higher-elevation features on the back side of the fabrication substrate. Semiconductor devices with transistors on the active surface and contact plugs that extend through the substrate are also disclosed, as are electronic devices including such semiconductor devices.
摘要翻译：用于制造诸如互补金属氧化物半导体（CMOS）成像器的半导体器件的方法包括在制造衬底的有源表面上制造晶体管和其它低仰角特征，以及制造接触插塞，导线，外部触点等在制造基板的背面上的较高高度特征。还公开了在有源表面上具有晶体管的半导体器件和延伸穿过衬底的接触插塞，以及包括这种半导体器件的电子器件也是公开的。

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