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1. 发明授权

US09646899B2 Interconnect assemblies with probed bond pads 有权
公开(公告)号：US09646899B2
公开(公告)日：2017-05-09
申请号：US13614286
申请日：2012-09-13
申请人： Owen R. Fay , Kyle K. Kirby , Luke G. England , Jaspreet S. Gandhi
发明人： Owen R. Fay , Kyle K. Kirby , Luke G. England , Jaspreet S. Gandhi
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/66 , H01L23/00
CPC分类号： H01L22/32 , H01L22/14 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02163 , H01L2224/0391 , H01L2224/0392 , H01L2224/0401 , H01L2224/05567 , H01L2224/05624 , H01L2224/13005 , H01L2224/13012 , H01L2224/13013 , H01L2224/13018 , H01L2224/13022 , H01L2224/13083 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/1461 , H01L2924/00012 , H01L2924/206 , H01L2924/01047 , H01L2924/00 , H01L2224/05552
摘要： An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.

2. 发明授权

US08753981B2 Microelectronic devices with through-silicon vias and associated methods of manufacturing 有权
标题翻译：具有通硅通孔和相关制造方法的微电子器件
公开(公告)号：US08753981B2
公开(公告)日：2014-06-17
申请号：US13092434
申请日：2011-04-22
申请人： Kyle K. Kirby , Kunal R. Parekh , Philip J. Ireland , Sarah A. Niroumand
发明人： Kyle K. Kirby , Kunal R. Parekh , Philip J. Ireland , Sarah A. Niroumand
IPC分类号： H01L21/44 , H01L21/311
CPC分类号： H01L23/5226 , H01L21/02063 , H01L21/76843 , H01L21/76898 , H01L23/481 , H01L23/528 , H01L23/53238 , H01L23/53266 , H01L23/53271 , H01L2224/13025 , H01L2924/00013 , H01L2924/0002 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an opening having a sidewall such that the opening extends through at least a portion of a substrate on which microelectronic structures have been formed. The method can further include lining the sidewall with a dielectric material, depositing tungsten on the dielectric material such that a cavity extends through at least a portion of the tungsten, and filling the cavity with a polysilicon material.
摘要翻译：具有通硅通孔的微电子器件及其相关制造方法。一种用于形成钨硅通孔的方法的一个实施例，包括形成具有侧壁的开口，使得所述开口延伸穿过已经形成有微电子结构的衬底的至少一部分。该方法可以进一步包括用介电材料衬里侧壁，在介电材料上沉积钨，使得空腔延伸穿过钨的至少一部分，并用多晶硅材料填充空腔。

3. 发明申请

US20140070832A1 INTERCONNECT ASSEMBLIES WITH PROBED BOND PADS 有权
标题翻译：互连组装与探测的粘结垫
公开(公告)号：US20140070832A1
公开(公告)日：2014-03-13
申请号：US13614286
申请日：2012-09-13
申请人： Owen R. Fay , Kyle K. Kirby , Luke G. England , Jaspreet S. Gandhi
发明人： Owen R. Fay , Kyle K. Kirby , Luke G. England , Jaspreet S. Gandhi
IPC分类号： G01R1/067
CPC分类号： H01L22/32 , H01L22/14 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02163 , H01L2224/0391 , H01L2224/0392 , H01L2224/0401 , H01L2224/05567 , H01L2224/05624 , H01L2224/13005 , H01L2224/13012 , H01L2224/13013 , H01L2224/13018 , H01L2224/13022 , H01L2224/13083 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/1461 , H01L2924/00012 , H01L2924/206 , H01L2924/01047 , H01L2924/00 , H01L2224/05552
摘要： An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.
摘要翻译：互连组件包括接合焊盘和配置为将电子结构电耦合到接合焊盘的互连结构。互连结构物理地接触位于可能在测试期间损坏的探针接触区域外部的接合焊盘的区域。绝缘材料覆盖探针接触区域并且限定与探针接触区域间隔开的开口。互连结构延伸穿过开口以接触接合焊盘。

4. 发明授权

US08531046B2 Semiconductor substrates comprising through substrate interconnects that are visible on the substrate backside 有权
标题翻译：包括在衬底背面可见的通过衬底互连的半导体衬底
公开(公告)号：US08531046B2
公开(公告)日：2013-09-10
申请号：US13099672
申请日：2011-05-03
申请人： Dave Pratt , Kyle K. Kirby , Steve Oliver , Mark Hiatt
发明人： Dave Pratt , Kyle K. Kirby , Steve Oliver , Mark Hiatt
IPC分类号： H01L23/544
CPC分类号： H01L21/682 , H01L21/67259 , H01L21/76898 , H01L23/544 , H01L2223/5442 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated.
摘要翻译：本发明包括确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件。在一个实现中，确定包括集成电路的半导体衬底的x-y空间取向的方法包括提供包括至少一个集成电路管芯的半导体衬底。半导体衬底包括电路侧，背面以及从电路侧延伸到背面的多个导电通路。检查半导体衬底背面上的多个导电通孔以确定半导体衬底背面上的多个导电通孔中的至少两个的部分的位置。从确定的位置确定半导体衬底的x-y空间取向。考虑了其他方面和实现。

5. 发明申请

US20120309128A1 DISABLING ELECTRICAL CONNECTIONS USING PASS-THROUGH 3D INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS 有权
标题翻译：使用通过三维互连和关联系统和方法禁用电气连接
公开(公告)号：US20120309128A1
公开(公告)日：2012-12-06
申请号：US13572461
申请日：2012-08-10
申请人： Jeffery W. Janzen , Russell D. Slifer , Michael Chaine , Kyle K. Kirby , William M. Hiatt
发明人： Jeffery W. Janzen , Russell D. Slifer , Michael Chaine , Kyle K. Kirby , William M. Hiatt
IPC分类号： H01L21/50 , H01L21/768
CPC分类号： H01L23/481 , H01L21/50 , H01L21/76898 , H01L21/82 , H01L23/52 , H01L23/525 , H01L23/60 , H01L23/62 , H01L24/17 , H01L25/0657 , H01L25/50 , H01L27/0248 , H01L2224/02372 , H01L2224/0401 , H01L2224/13009 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17051 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06593 , H01L2924/13034 , H01L2924/00014
摘要： Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.
摘要翻译：本文公开了直通3D互连和微电子管芯以及包括这种互连以禁用电连接的堆叠管芯的系统。在一个实施例中，堆叠管芯的系统包括具有背面的第一微电子管芯，经由第一管芯延伸到背面的互连件，电耦合到互连的集成电路，以及与第一静电放电（ESD）器件电隔离的第一静电放电互连。第二微电子管芯具有耦合到第一管芯的背侧的前侧，电连接到互连的前侧的金属接触件和电耦合到金属接触件的第二ESD器件。在另一实施例中，第一管芯还包括承载集成电路和第一ESD器件的衬底，并且互连件位于衬底中，以禁止第一ESD器件和互连件之间的电连接。

6. 发明申请

US20120068348A1 Interconnect Regions 有权
标题翻译：互连区域
公开(公告)号：US20120068348A1
公开(公告)日：2012-03-22
申请号：US12886199
申请日：2010-09-20
申请人： Kyle K. Kirby , Philip J. Ireland
发明人： Kyle K. Kirby , Philip J. Ireland
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L21/7682 , H01L23/481 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： Some embodiments include interconnect regions. The regions may contain, along a cross section, a closed-shape interior region having an electrically conductive material therein, a first dielectric material configured as a liner extending entirely around a lateral periphery of the interior region, and at least two dielectric projections joining to the dielectric material liner and being laterally outward of the interior region. The dielectric projections may have an outer dielectric ring surrounding an inner dielectric region. The outer ring may consist of the first dielectric material and the inner dielectric region may be a composition different from a composition of the first dielectric material, and in some embodiments the composition within the inner dielectric region may be gaseous.
摘要翻译：一些实施例包括互连区域。这些区域可以沿着横截面包含其中具有导电材料的封闭形状的内部区域，被配置为完全围绕内部区域的侧边缘延伸的衬垫的第一介电材料和至少两个介电突起，电介质材料衬里并且在内部区域的横向外侧。电介质突起可以具有围绕内部电介质区域的外部介电环。外环可以由第一介电材料组成，并且内介电区可以是不同于第一介电材料的组成的组成，在一些实施例中，内介电区内的组成可以是气态的。

7. 发明授权

US07960829B2 Support structure for use in thinning semiconductor substrates and for supporting thinned semiconductor substrates 有权
标题翻译：用于减薄半导体衬底和用于支撑薄化半导体衬底的支撑结构
公开(公告)号：US07960829B2
公开(公告)日：2011-06-14
申请号：US11216617
申请日：2005-08-31
申请人： Alan G. Wood , Warren M. Farnworth , David R. Hembree , Sidney B. Rigg , William M. Hiatt , Peter Benson , Kyle K. Kirby , Salman Akram
发明人： Alan G. Wood , Warren M. Farnworth , David R. Hembree , Sidney B. Rigg , William M. Hiatt , Peter Benson , Kyle K. Kirby , Salman Akram
IPC分类号： H01L23/12
CPC分类号： G03F7/0037 , B33Y30/00 , B33Y70/00 , B33Y80/00 , G03F7/0047
摘要： A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion that extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member that substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface.
摘要翻译：用于半导体衬底的减薄或后研磨以及在半导体衬底的后变薄处理期间的支撑结构包括基本上沿着半导体衬底的外周延伸并围绕半导体衬底的外周延伸的部分，以使半导体衬底基板具有刚性。支撑结构可以被构造为环或作为基本上覆盖半导体衬底的有源表面并且在由有源表面承载的每个半导体器件上形成保护结构的构件。

8. 发明授权

US07956443B2 Through-wafer interconnects for photoimager and memory wafers 有权
标题翻译：用于光刻机和存储晶圆的透晶片互连
公开(公告)号：US07956443B2
公开(公告)日：2011-06-07
申请号：US12725724
申请日：2010-03-17
申请人： Salman Akram , Charles M. Watkins , Mark Hiatt , David R. Hembree , James M. Wark , Warren M. Farnworth , Mark E. Tuttle , Sidney B. Rigg , Steven D. Oliver , Kyle K. Kirby , Alan G. Wood , Lu Velicky
发明人： Salman Akram , Charles M. Watkins , Mark Hiatt , David R. Hembree , James M. Wark , Warren M. Farnworth , Mark E. Tuttle , Sidney B. Rigg , Steven D. Oliver , Kyle K. Kirby , Alan G. Wood , Lu Velicky
IPC分类号： H01L23/485
CPC分类号： H01L21/76877 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/45 , H01L27/14634 , H01L27/14636 , H01L2221/6834 , H01L2224/02166 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
摘要翻译：公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

9. 发明授权

US07919348B2 Methods for protecting imaging elements of photoimagers during back side processing 有权
标题翻译：用于在背面处理期间保护光成像器的成像元件的方法
公开(公告)号：US07919348B2
公开(公告)日：2011-04-05
申请号：US12139068
申请日：2008-06-13
申请人： Salman Akram , Kyle K. Kirby
发明人： Salman Akram , Kyle K. Kirby
IPC分类号： H01L21/00
CPC分类号： H01L27/14618 , H01L27/14636 , H01L27/14685 , H01L2224/13
摘要： Methods for processing photoimagers include forming one or more protective layers over the image sensing elements of a photoimager. Protective layers may facilitate thinning of the substrates of photoimagers, as well as prevent contamination of the image sensing elements and associated optical features during back side processing of the photoimagers. Blind vias, which extend from the back side of a photoimager to bond pads carried by an active surface of the photoimager, may be formed through the back side. The vias may be filled with conductive material and, optionally, redistribution circuitry may be fabricated over the back side of the photoimager. Photoimagers including features at result from such processes are also disclosed.
摘要翻译：用于处理光影目标的方法包括在光成像仪的图像感测元件上形成一个或多个保护层。保护层可以促进光刻胶的基材的变薄，并且可以防止在光成像器的背面处理期间图像感测元件和相关的光学特征的污染。可以通过背面形成从光电成像仪的背面延伸到由光电成像仪的有源表面承载的接合焊盘的盲通孔。通孔可以用导电材料填充，并且可选地，重新分布电路可以在光电成像仪的背面上制造。还公开了包括这些处理结果的特征的光照器。

10. 发明申请

US20110042821A1 VIAS AND CONDUCTIVE ROUTING LAYERS IN SEMICONDUCTOR SUBSTRATES 有权
标题翻译：半导体衬底中的VIAS和导电路由层
公开(公告)号：US20110042821A1
公开(公告)日：2011-02-24
申请号：US12545196
申请日：2009-08-21
申请人： Kyle K. Kirby , Sarah A. Niroumand
发明人： Kyle K. Kirby , Sarah A. Niroumand
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/16 , H01L2224/0401 , H01L2224/05025 , H01L2224/13025 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/3025 , H01L2924/00
摘要： Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method for processing a semiconductor substrate includes forming an aperture in a semiconductor substrate and through a dielectric on the semiconductor substrate. The aperture has a first end open at the dielectric and a second end opposite the first end. The method can also include forming a plurality of depressions in the dielectric, and simultaneously depositing a conductive material into the aperture and at least some of the depressions.
摘要翻译：本文公开了半导体衬底中的通孔和导电布线层以及相关的制造方法。在一个实施例中，一种用于处理半导体衬底的方法包括在半导体衬底中形成孔，并通过半导体衬底上的电介质。开口具有在电介质处开放的第一端和与第一端相对的第二端。该方法还可以包括在电介质中形成多个凹陷，并且同时将导电材料沉积到孔和至少一些凹陷中。

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