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1. 发明授权

US08531046B2 Semiconductor substrates comprising through substrate interconnects that are visible on the substrate backside 有权
标题翻译：包括在衬底背面可见的通过衬底互连的半导体衬底
公开(公告)号：US08531046B2
公开(公告)日：2013-09-10
申请号：US13099672
申请日：2011-05-03
申请人： Dave Pratt , Kyle K. Kirby , Steve Oliver , Mark Hiatt
发明人： Dave Pratt , Kyle K. Kirby , Steve Oliver , Mark Hiatt
IPC分类号： H01L23/544
CPC分类号： H01L21/682 , H01L21/67259 , H01L21/76898 , H01L23/544 , H01L2223/5442 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated.
摘要翻译：本发明包括确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件。在一个实现中，确定包括集成电路的半导体衬底的x-y空间取向的方法包括提供包括至少一个集成电路管芯的半导体衬底。半导体衬底包括电路侧，背面以及从电路侧延伸到背面的多个导电通路。检查半导体衬底背面上的多个导电通孔以确定半导体衬底背面上的多个导电通孔中的至少两个的部分的位置。从确定的位置确定半导体衬底的x-y空间取向。考虑了其他方面和实现。

2. 发明申请

US20110204526A1 Methods of Determining X-Y Spatial Orientation of a Semiconductor Substrate Comprising an Integrated Circuit, Methods of Positioning a Semiconductor Substrate Comprising an Integrated Circuit, Methods of Processing a Semiconductor Substrate, and Semiconductor Devices 有权
标题翻译：确定包含集成电路的半导体衬底的X-Y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法和半导体器件
公开(公告)号：US20110204526A1
公开(公告)日：2011-08-25
申请号：US13099672
申请日：2011-05-03
申请人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
发明人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
IPC分类号： H01L23/48
CPC分类号： H01L21/682 , H01L21/67259 , H01L21/76898 , H01L23/544 , H01L2223/5442 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated.
摘要翻译：本发明包括确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件。在一个实现中，确定包括集成电路的半导体衬底的x-y空间取向的方法包括提供包括至少一个集成电路管芯的半导体衬底。半导体衬底包括电路侧，背面以及从电路侧延伸到背面的多个导电通路。检查半导体衬底背面上的多个导电通孔以确定半导体衬底背面上的多个导电通孔中的至少两个的部分的位置。从确定的位置确定半导体衬底的x-y空间取向。考虑了其他方面和实现。

3. 发明授权

US07955946B2 Methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices 有权
标题翻译：确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件
公开(公告)号：US07955946B2
公开(公告)日：2011-06-07
申请号：US11439078
申请日：2006-05-22
申请人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
发明人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
IPC分类号： H01L21/76
CPC分类号： H01L21/682 , H01L21/67259 , H01L21/76898 , H01L23/544 , H01L2223/5442 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated.
摘要翻译：本发明包括确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法和半导体器件。在一个实现中，确定包括集成电路的半导体衬底的x-y空间取向的方法包括提供包括至少一个集成电路管芯的半导体衬底。半导体衬底包括电路侧，背面以及从电路侧延伸到背面的多个导电通路。检查半导体衬底背面上的多个导电通孔以确定半导体衬底背面上的多个导电通孔中的至少两个的部分的位置。从确定的位置确定半导体衬底的x-y空间取向。考虑了其他方面和实现。

4. 发明申请

US20070269994A1 Methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices 有权
标题翻译：确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件
公开(公告)号：US20070269994A1
公开(公告)日：2007-11-22
申请号：US11439078
申请日：2006-05-22
申请人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
发明人： Dave Pratt , Kyle Kirby , Steve Oliver , Mark Hiatt
IPC分类号： H01L21/00
CPC分类号： H01L21/682 , H01L21/67259 , H01L21/76898 , H01L23/544 , H01L2223/5442 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated.
摘要翻译：本发明包括确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件。在一个实现中，确定包括集成电路的半导体衬底的x-y空间取向的方法包括提供包括至少一个集成电路管芯的半导体衬底。半导体衬底包括电路侧，背面以及从电路侧延伸到背面的多个导电通路。检查半导体衬底背面上的多个导电通孔以确定半导体衬底背面上的多个导电通孔中的至少两个的部分的位置。从确定的位置确定半导体衬底的x-y空间取向。考虑了其他方面和实现。

5. 发明申请

US20120286424A1 DIE STACKING WITH AN ANNULAR VIA HAVING A RECESSED SOCKET 有权
标题翻译：通过具有接合插座的封装进行封装
公开(公告)号：US20120286424A1
公开(公告)日：2012-11-15
申请号：US13556026
申请日：2012-07-23
申请人： Dave Pratt
发明人： Dave Pratt
IPC分类号： H01L21/768 , H01L23/48 , H01L23/498
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/1147 , H01L2224/13025 , H01L2224/13099 , H01L2224/13147 , H01L2224/16147 , H01L2224/16235 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2225/06513 , H01L2225/06541 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a variety of electronic systems. In an embodiment, a die stack includes a conductive pillar on the top of a die inserted into the recessed conductive socket of another die.
摘要翻译：包括具有带凹入的导电插座的环形通孔的模具的模具堆叠和形成模具叠层的方法提供了用于各种电子系统的结构。在一个实施例中，管芯堆叠包括在插入到另一管芯的凹入的导电插座中的管芯的顶部上的导电柱。

6. 发明申请

US20110031632A1 DIE STACKING WITH AN ANNULAR VIA HAVING A RECESSED SOCKET 有权
标题翻译：通过具有接合插座的封装进行封装
公开(公告)号：US20110031632A1
公开(公告)日：2011-02-10
申请号：US12905708
申请日：2010-10-15
申请人： Dave Pratt
发明人： Dave Pratt
IPC分类号： H01L23/498 , H01L21/50 , H01L21/768
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/1147 , H01L2224/13025 , H01L2224/13099 , H01L2224/13147 , H01L2224/16147 , H01L2224/16235 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2225/06513 , H01L2225/06541 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a variety of electronic systems. In an embodiment, a die stack includes a conductive pillar on the top of a die inserted into the recessed conductive socket of another die.
摘要翻译：包括具有带凹入的导电插座的环形通孔的模具的模具堆叠和形成模具叠层的方法提供了用于各种电子系统的结构。在一个实施例中，管芯堆叠包括在插入到另一管芯的凹入的导电插座中的管芯的顶部上的导电柱。

7. 发明授权

US07821107B2 Die stacking with an annular via having a recessed socket 有权
标题翻译：具有凹入插座的环形通孔的芯片堆叠
公开(公告)号：US07821107B2
公开(公告)日：2010-10-26
申请号：US12107576
申请日：2008-04-22
申请人： Dave Pratt
发明人： Dave Pratt
IPC分类号： H01L29/40
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/1147 , H01L2224/13025 , H01L2224/13099 , H01L2224/13147 , H01L2224/16147 , H01L2224/16235 , H01L2224/16237 , H01L2224/81141 , H01L2224/81191 , H01L2225/06513 , H01L2225/06541 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a variety of electronic systems. In an embodiment, a die stack includes a conductive pillar on the top of a die inserted into the recessed conductive socket of another die.
摘要翻译：包括具有带凹入的导电插座的环形通孔的模具的模具堆叠和形成模具叠层的方法提供了用于各种电子系统的结构。在一个实施例中，管芯堆叠包括在插入到另一管芯的凹入的导电插座中的管芯的顶部上的导电柱。

8. 发明申请

US20090255705A1 Method of Creating Alignment/Centering Guides for Small Diameter, High Density Through-Wafer Via Die Stacking 有权
标题翻译：通过模具堆叠创建小直径，高密度通过晶片的对准/定心导轨的方法
公开(公告)号：US20090255705A1
公开(公告)日：2009-10-15
申请号：US12101776
申请日：2008-04-11
申请人： Dave Pratt
发明人： Dave Pratt
IPC分类号： H02G3/00 , H01R43/00
CPC分类号： H01L25/50 , H01L23/481 , H01L24/12 , H01L24/81 , H01L25/0657 , H01L2224/10135 , H01L2224/10165 , H01L2224/13009 , H01L2224/13099 , H01L2224/13147 , H01L2224/8014 , H01L2224/81136 , H01L2224/81139 , H01L2224/8114 , H01L2224/81141 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , Y10T29/49117
摘要： A method if provided for forming a die stack. The method includes forming a plurality of through-wafer vias and a first plurality of alignment features in a first die. A second plurality of alignment features is formed in a second die, and the first die is stacked on the second die such that the first plurality of alignment features engage the second plurality of alignment features. A method of manufacturing a die stack is also provided that includes forming a plurality of through-wafer vias on a first die, forming a plurality of recesses on a first die, and forming a plurality of protrusions on a second die. A die stack and a system are also provided.
摘要翻译：提供用于形成管芯叠层的方法。该方法包括在第一管芯中形成多个贯通晶片通孔和第一多个对准特征。在第二模具中形成第二多个对准特征，并且第一模具被堆叠在第二模具上，使得第一多个对准特征接合第二多个对准特征。还提供了一种制造管芯叠层的方法，其包括在第一管芯上形成多个贯通晶片通孔，在第一管芯上形成多个凹槽，以及在第二管芯上形成多个突起。还提供了模具堆叠和系统。

9. 发明申请

US20090047781A1 Methods of Forming Through Substrate Interconnects 有权
标题翻译：通过基板互连形成的方法
公开(公告)号：US20090047781A1
公开(公告)日：2009-02-19
申请号：US11840120
申请日：2007-08-16
申请人： Dave Pratt , Andy Perkins
发明人： Dave Pratt , Andy Perkins
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L21/02282 , H01L21/76831
摘要： A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.
摘要翻译：形成贯穿基板互连的方法包括将通孔形成为半导体基板。通孔延伸到基板的半导体材料中。施加液体电介质以将通孔的侧壁的至少顶部最外部分相对于基底的最初形成通孔的一侧排列。液体电介质在通孔内固化。导电材料形成在固化电介质上的通孔中，并且通过基板互连形成有导电材料。

10. 发明授权

US08034702B2 Methods of forming through substrate interconnects 有权
标题翻译：通过衬底互连形成的方法
公开(公告)号：US08034702B2
公开(公告)日：2011-10-11
申请号：US11840120
申请日：2007-08-16
申请人： Dave Pratt , Andy Perkins
发明人： Dave Pratt , Andy Perkins
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L21/02282 , H01L21/76831
摘要： A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.
摘要翻译：形成贯穿基板互连的方法包括将通孔形成为半导体基板。通孔延伸到基板的半导体材料中。施加液体电介质以将通孔的侧壁的至少顶部最外部分相对于基底的最初形成通孔的一侧排列。液体电介质在通孔内固化。导电材料形成在固化电介质上的通孔中，并且通过基板互连形成有导电材料。

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