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1. 发明申请

US20110095429A1 METHODS FOR FABRICATING AND FILLING CONDUCTIVE VIAS AND CONDUCTIVE VIAS SO FORMED 有权
标题翻译：制造和填充导电VIAS和导电VIAS的方法
公开(公告)号：US20110095429A1
公开(公告)日：2011-04-28
申请号：US12985570
申请日：2011-01-06
申请人： Salman Akram , William Mark Hiatt , Steve Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
发明人： Salman Akram , William Mark Hiatt , Steve Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
IPC分类号： H01L23/48 , H01L23/532
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/17181 , H01L2924/09701
摘要： Methods for forming conductive vias include foiling one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof A barrier layer may be fowled over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.
摘要翻译：用于形成导电通孔的方法包括在基板中形成一个或多个通孔。通孔可以形成有单个掩模，其中在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其它特征用作硬掩模。通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。阻挡层可以在每个通孔的表面上被覆盖。可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

2. 发明授权

US07892972B2 Methods for fabricating and filling conductive vias and conductive vias so formed 有权
标题翻译：制造和填充如此形成的导电通孔和导电通孔的方法
公开(公告)号：US07892972B2
公开(公告)日：2011-02-22
申请号：US11347153
申请日：2006-02-03
申请人： Salman Akram , William Mark Hiatt , Steve Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
发明人： Salman Akram , William Mark Hiatt , Steve Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/17181 , H01L2924/09701
摘要： Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.
摘要翻译：用于形成导电通孔的方法包括在衬底中形成一个或多个通孔。通孔可以形成有单个掩模，其中在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其它特征用作硬掩模。通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。可以在每个通孔的表面上形成阻挡层。可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

3. 发明授权

US07683458B2 Through-wafer interconnects for photoimager and memory wafers 失效
标题翻译：用于光刻机和存储晶圆的透晶片互连
公开(公告)号：US07683458B2
公开(公告)日：2010-03-23
申请号：US11924781
申请日：2007-10-26
申请人： Salman Akram , Charles M. Watkins , William M. Hiatt , David R. Hembree , James M. Wark , Warren M. Farnworth , Mark E. Tuttle , Sidney B. Rigg , Steven D. Oliver , Kyle K. Kirby , Alan G. Wood , Lu Velicky
发明人： Salman Akram , Charles M. Watkins , William M. Hiatt , David R. Hembree , James M. Wark , Warren M. Farnworth , Mark E. Tuttle , Sidney B. Rigg , Steven D. Oliver , Kyle K. Kirby , Alan G. Wood , Lu Velicky
IPC分类号： H01L23/485
CPC分类号： H01L21/76877 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/45 , H01L27/14634 , H01L27/14636 , H01L2221/6834 , H01L2224/02166 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
摘要翻译：公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

4. 发明申请

US20090191701A1 MICROELECTRONIC DEVICES AND METHODS FOR FORMING INTERCONNECTS IN MICROELECTRONIC DEVICES 有权
标题翻译：用于在微电子设备中形成互连的微电子器件和方法
公开(公告)号：US20090191701A1
公开(公告)日：2009-07-30
申请号：US12419029
申请日：2009-04-06
申请人： Kyle K. Kirby , Salman Akram , David R. Hembree , Sidney B. Rigg , Warren M. Farnworth , William M. Hiatt
发明人： Kyle K. Kirby , Salman Akram , David R. Hembree , Sidney B. Rigg , Warren M. Farnworth , William M. Hiatt
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/48 , H01L2224/48091 , H01L2224/48465 , H01L2924/00014 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H05K1/0306 , H05K3/4038 , H05K3/422 , H05K3/423 , H05K2201/0305 , H05K2201/09827 , H05K2203/072 , H05K2203/1147 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.
摘要翻译：本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微电子器件中形成互连的方法。在一个实施例中，一种方法包括提供具有正面和背面的微电子衬底。衬底具有包括集成电路的微电子管芯和可操作地耦合到集成电路的端子。该方法还包括至少部分地形成通过基底并且在基底的前侧和/或后侧具有开口的通道。该方法还包括用封闭通道一端的导电盖密封开口，同时通道的另一端保持打开。该方法然后包括用导电材料填充通道。

5. 发明授权

US07329943B2 Microelectronic devices and methods for forming interconnects in microelectronic devices 有权
标题翻译：用于在微电子器件中形成互连的微电子器件和方法
公开(公告)号：US07329943B2
公开(公告)日：2008-02-12
申请号：US11416824
申请日：2006-05-03
申请人： Kyle K. Kirby , Salman Akram , David R. Hembree , Sidney B. Rigg , Warren M. Farnworth , William M. Hiatt
发明人： Kyle K. Kirby , Salman Akram , David R. Hembree , Sidney B. Rigg , Warren M. Farnworth , William M. Hiatt
IPC分类号： H01L29/40
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/48 , H01L2224/48091 , H01L2224/48465 , H01L2924/00014 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H05K1/0306 , H05K3/4038 , H05K3/422 , H05K3/423 , H05K2201/0305 , H05K2201/09827 , H05K2203/072 , H05K2203/1147 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.
摘要翻译：本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微电子器件中形成互连的方法。在一个实施例中，一种方法包括提供具有正面和背面的微电子衬底。衬底具有包括集成电路的微电子管芯和可操作地耦合到集成电路的端子。该方法还包括至少部分地形成通过基底并且在基底的前侧和/或后侧具有开口的通道。该方法还包括用封闭通道一端的导电盖密封开口，同时通道的另一端保持打开。该方法然后包括用导电材料填充通道。

6. 发明授权

US07265330B2 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers 有权
标题翻译：具有光学器件的微电子成像器和制造这种微电子成像器的方法
公开(公告)号：US07265330B2
公开(公告)日：2007-09-04
申请号：US11476015
申请日：2006-06-28
申请人： Warren M. Farnworth , Sidney B. Rigg , William Mark Hiatt , Alan G. Wood , Peter A. Benson , James M. Wark , David R. Hembree , Kyle K. Kirby , Charles M. Watkins , Salman Akram
发明人： Warren M. Farnworth , Sidney B. Rigg , William Mark Hiatt , Alan G. Wood , Peter A. Benson , James M. Wark , David R. Hembree , Kyle K. Kirby , Charles M. Watkins , Salman Akram
IPC分类号： H01L27/00 , H01L31/0232
CPC分类号： H01L27/00 , B33Y80/00 , H01L27/14618 , H01L27/14625 , H01L27/14683 , H01L27/14687 , H01L2224/48091 , H01L2224/48227 , H01L2924/01077 , H01L2924/01078 , H01L2924/00014
摘要： Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.
摘要翻译：微电子成像器组件包括包括衬底的工件和在衬底上和/或衬底中的多个成像管芯。基板包括前侧和后侧，并且成像管芯包括在基板的前侧的成像传感器和可操作地耦合到图像传感器的外部触点。微电子成像器组件还包括相对于成像管芯叠加的光学支架。光学支撑件可以直接在基板上或衬底上的盖上。单个光学支撑件可以具有（a）与图像传感器中的一个对准的开口，以及（b）与图像传感器相距一定距离处的轴承元件。微电子成像器组件还可以包括由光学器件支撑件安装或以其它方式承载的光学器件。

7. 发明授权

US07232754B2 Microelectronic devices and methods for forming interconnects in microelectronic devices 有权
标题翻译：用于在微电子器件中形成互连的微电子器件和方法
公开(公告)号：US07232754B2
公开(公告)日：2007-06-19
申请号：US10879838
申请日：2004-06-29
申请人： Kyle K. Kirby , Salman Akram , David R. Hembree , Sidney B. Rigg , Warren M. Farnworth , William M. Hiatt
发明人： Kyle K. Kirby , Salman Akram , David R. Hembree , Sidney B. Rigg , Warren M. Farnworth , William M. Hiatt
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/48 , H01L2224/48091 , H01L2224/48465 , H01L2924/00014 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H05K1/0306 , H05K3/4038 , H05K3/422 , H05K3/423 , H05K2201/0305 , H05K2201/09827 , H05K2203/072 , H05K2203/1147 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.
摘要翻译：本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微电子器件中形成互连的方法。在一个实施例中，一种方法包括提供具有正面和背面的微电子衬底。衬底具有包括集成电路的微电子管芯和可操作地耦合到集成电路的端子。该方法还包括至少部分地形成通过基底并且在基底的前侧和/或后侧具有开口的通道。该方法还包括用封闭通道一端的导电盖密封开口，同时通道的另一端保持打开。该方法然后包括用导电材料填充通道。

8. 发明授权

US06595832B2 Chemical mechanical polishing methods 有权
标题翻译：化学机械抛光方法
公开(公告)号：US06595832B2
公开(公告)日：2003-07-22
申请号：US09789324
申请日：2001-02-20
申请人： Michael J. Joslyn , Sidney B. Rigg
发明人： Michael J. Joslyn , Sidney B. Rigg
IPC分类号： B24B100
CPC分类号： H01L21/31053 , B24B37/04 , B24B37/042
摘要： In one implementation, a chemical mechanical polishing method includes providing a workpiece having a dielectric region to be polished. A first chemical mechanical polishing of the dielectric region is conducted on the workpiece using a polishing pad and a first slurry. Then, a second chemical mechanical polishing is conducted of the dielectric region on the workpiece using the polishing pad and a second slurry different from the first slurry. In one implementation, a chemical mechanical polishing method includes providing a workpiece having a dielectric region to be polished. The dielectric region has a thickness ultimately desired to removed by polishing prior to moving the workpiece on to a subsequent nonpolishing processing step. A first chemical mechanical polishing of the dielectric region is conducted on the workpiece using a first slurry. Then, a second chemical mechanical polishing of the dielectric region is conducted on the workpiece using a second slurry different from the first slurry. The second chemical mechanical polishing removes at least 15% of the thickness.
摘要翻译：在一个实施方案中，化学机械抛光方法包括提供具有待抛光的电介质区域的工件。使用抛光垫和第一浆料在工件上进行电介质区域的第一化学机械抛光。然后，使用抛光垫和不同于第一浆料的第二浆料，对工件上的电介质区域进行第二化学机械抛光。在一个实施方案中，化学机械抛光方法包括提供具有待抛光的电介质区域的工件。在将工件移动到随后的非抛光处理步骤之前，电介质区域具有最终希望通过抛光去除的厚度。使用第一浆料在工件上进行电介质区域的第一化学机械抛光。然后，使用与第一浆料不同的第二浆料，在工件上进行电介质区域的第二化学机械抛光。第二次化学机械抛光去除厚度的至少15％。

9. 发明申请

US20110272806A1 SEMICONDUCTOR DICE INCLUDING AT LEAST ONE BLIND HOLE, WAFERS INCLUDING SUCH SEMICONDUCTOR DICE, AND INTERMEDIATE PRODUCTS MADE WHILE FORMING AT LEAST ONE BLIND HOLE IN A SUBSTRATE 有权
标题翻译：半导体芯片包括至少一个盲孔，包括这样的半导体晶片的晶片，以及在基板中形成至少一个盲孔的中间产品
公开(公告)号：US20110272806A1
公开(公告)日：2011-11-10
申请号：US13187133
申请日：2011-07-20
申请人： Salman Akram , Sidney B. Rigg
发明人： Salman Akram , Sidney B. Rigg
IPC分类号： H01L23/498 , H01L23/485 , H01L23/48
CPC分类号： H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05572 , H01L2224/06181 , H01L2224/13022 , H01L2224/13025 , H01L2224/16 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/15311 , H01L2924/00012 , H01L2224/05552
摘要： Semiconductor dice comprise at least one bond pad on an active surface of the semiconductor die. At least one blind hole extends from a back surface of the semiconductor die opposing the active surface, through a thickness of the semiconductor die, to an underside of the at least one bond pad. At least one quantity of passivation material covers at least a sidewall surface of the at least one blind hole. At least one conductive material is disposed in the at least one blind hole adjacent and in electrical communication with the at least one bond pad and adjacent the at least one quantity of passivation material.
摘要翻译：半导体管芯包括在半导体管芯的有效表面上的至少一个接合焊盘。至少一个盲孔从所述半导体管芯的与所述有源表面相反的后表面延伸穿过所述半导体管芯的厚度到所述至少一个接合焊盘的下侧。至少一个量的钝化材料覆盖至少一个盲孔的至少一侧壁表面。至少一个导电材料设置在所述至少一个盲孔中，与所述至少一个接合焊盘相邻并与所述至少一个焊接焊盘相邻并且与所述至少一个量的钝化材料相邻。

10. 发明授权

US07989345B2 Methods of forming blind wafer interconnects, and related structures and assemblies 有权
标题翻译：形成盲晶片互连的方法以及相关的结构和组件
公开(公告)号：US07989345B2
公开(公告)日：2011-08-02
申请号：US11776137
申请日：2007-07-11
申请人： Salman Akram , Sidney B. Rigg
发明人： Salman Akram , Sidney B. Rigg
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05572 , H01L2224/06181 , H01L2224/13022 , H01L2224/13025 , H01L2224/16 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/15311 , H01L2924/00012 , H01L2224/05552
摘要： Methods for forming blind wafer interconnects (BWIs) from the back side surface of a substrate structure to the underside of a bond pad on the opposing surface includes the formation of a blind hole from the back side surface, forming a passivating layer therein, removing passivation material from the blind hole bottom, depositing at least one conductive layer within the blind hole, and filling the blind hole with solder or other conductive material or a dielectric material.
摘要翻译：用于从基板结构的背面形成到相对表面上的接合焊盘的下侧的盲晶片互连（BWI）的形成方法包括从背面形成盲孔，在其中形成钝化层，去除钝化从盲孔底部的材料，在盲孔内沉积至少一个导电层，以及用焊料或其它导电材料或电介质材料填充盲孔。

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