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    • 1. 发明授权
      US6104064A Asymmetrical transistor structure 有权
    • Asymmetrical transistor structure
    • 不对称晶体管结构
    • US6104064A
    • 2000-08-15
    • US306508
    • 1999-05-06
    • Daniel Kadosh , Mark I. Gardner , Michael Duane , Jon D. Cheek , Fred N. Hause , Robert Dawson , Brad T. Moore
    • Daniel Kadosh , Mark I. Gardner , Michael Duane , Jon D. Cheek , Fred N. Hause , Robert Dawson , Brad T. Moore
    • H01L21/28 , H01L21/336 , H01L29/78 , H01L29/76
    • H01L21/28211 , H01L21/28176 , H01L29/66659 , H01L29/7835
    • Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.
    • 提供了用于产生p沟道和/或n沟道晶体管的各种工艺。 因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。 可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。 据此，本方法采用各种技术形成不对称晶体管。 各种技术采用根据​​所需LDD结果而变化的处理步骤。 首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。 第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。 漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。 第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。 可以存在许多其它修改和替代的处理步骤，其全部在此描述。 不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。 本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US5783458A Asymmetrical p-channel transistor having nitrided oxide patterned to allow select formation of a grown sidewall spacer 失效
    • Asymmetrical p-channel transistor having nitrided oxide patterned to allow select formation of a grown sidewall spacer
    • 具有氮化氧化物的非对称p沟道晶体管被图案化以允许选择形成生长侧壁间隔物
    • US5783458A
    • 1998-07-21
    • US720731
    • 1996-10-01
    • Daniel Kadosh , Robert Dawson , Fred N. Hause
    • Daniel Kadosh , Robert Dawson , Fred N. Hause
    • H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78 , H01L21/265 , H01L21/44
    • H01L21/28035 , H01L21/28176 , H01L29/4916 , H01L29/66659 , H01L29/7835 , H01L29/7836
    • Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current-a desirable outcome for high speed circuits.
    • 提供了用于产生p沟道和/或n沟道晶体管的各种工艺。 因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。 可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。 据此，本方法采用各种技术形成不对称晶体管。 各种技术采用根据​​所需LDD结果而变化的处理步骤。 首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。 第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。 漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。 第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。 可以存在许多其它修改和替代的处理步骤，其全部在此描述。 不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。 本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US6156649A Method of forming uniform sheet resistivity salicide 失效
    • Method of forming uniform sheet resistivity salicide
    • 形成均匀的电阻率自对准硅胶的方法
    • US6156649A
    • 2000-12-05
    • US60434
    • 1998-04-14
    • Fred N. Hause , Robert Dawson , Charles E. May
    • Fred N. Hause , Robert Dawson , Charles E. May
    • H01L21/28 , H01L21/285 , H01L21/336 , H01L21/44
    • H01L21/28518 , H01L21/28052 , H01L29/665
    • A semiconductor process in which a first silicide is formed on silicon upper surfaces upon which a second silicide is selectively deposited. A refractory metal is blanket deposited on a semiconductor substrate. The semiconductor substrate is then heated to a first temperature to react portions of the refractory metal above the exposed silicon surfaces to form a first phase of a first silicide. The unreacted portions of the refractory metal then remove, typically with a wet etch process. The semiconductor substrate is then heated to a second temperature to form a second phase of the first silicide. The second temperature is typically greater than the first, and the resistivity of the second phase is less than a resistivity of the first phase. Thereafter, a second metal silicide is selectively deposited on the first silicide, preferably through the use of a chemical vapor deposition process. In one embodiment, the selectively deposited second silicide is reacted with the existing first silicide to form a composite silicide structure exhibiting uniform sheet resistivity independent of the dimensions of the underlying silicon structure.
    • 一种半导体工艺，其中第一硅化物形成在硅上表面上，在其上选择性地沉积第二硅化物。 难熔金属被覆盖在半导体衬底上。 然后将半导体衬底加热至第一温度，以使暴露的硅表面上方的难熔金属的部分反应，以形成第一硅化物的第一相。 难熔金属的未反应部分通常用湿蚀刻工艺除去。 然后将半导体衬底加热至第二温度以形成第一硅化物的第二相。 第二温度通常大于第一温度，第二相的电阻率小于第一相的电阻率。 此后，优选通过使用化学气相沉积工艺，在第一硅化物上选择性地沉积第二金属硅化物。 在一个实施例中，选择性沉积的第二硅化物与现有的第一硅化物反应以形成独立于下面的硅结构的尺寸的均匀的薄层电阻的复合硅化物结构。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US5907764A In-line detection and assessment of net charge in PECVD silicon dioxide (oxide) layers 失效
    • In-line detection and assessment of net charge in PECVD silicon dioxide (oxide) layers
    • 在线检测和评估PECVD二氧化硅（氧化物）层中的净电荷
    • US5907764A
    • 1999-05-25
    • US556310
    • 1995-11-13
    • John K. Lowell , Fred N. Hause , Robert Dawson
    • John K. Lowell , Fred N. Hause , Robert Dawson
    • H01L21/316 , H01L21/66 , H01L21/302
    • H01L21/31612 , H01L21/02112 , H01L21/02274 , H01L22/14
    • The present method provides for the detection and assessment of the net charge in a PECVD oxide layer deposited on a surface of a semiconductor substrate. Electrical potential differences across PECVD oxide layers on as-produced semiconductor substrates are measured. Resultant PECVD oxide charge derivative values are plotted on an control chart and compared to calculated control parameters. All measurement techniques are non-contact and non-destructive, allowing them to be performed on as-processed semiconductor substrates at any time during or following a wafer fabrication process. In a first embodiment, a contact potential difference V.sub.CPD between a vibrating electrode and the semiconductor substrate is measured while the semiconductor substrate beneath the vibrating electrode is subjected to a constant beam of high intensity illumination. The resultant value of V.sub.CPD is equal to the electrical potential difference across the PECVD oxide layer V.sub.OX (plus a constant). In a second embodiment, the semiconductor substrate is not illuminated during the measurement of V.sub.CPD. A conventional SPV apparatus is used to measure the surface barrier potential V.sub.SP of the semiconductor substrate. Subtracting the measured value of V.sub.SP from the measured value of V.sub.CPD yields the value of V.sub.OX (plus a constant).
    • 本方法提供了在沉积在半导体衬底的表面上的PECVD氧化物层中的净电荷的检测和评估。 测量生成半导体衬底上的PECVD氧化物层的电位差。 将得到的PECVD氧化物电荷衍生值绘制在控制图上并与计算的控制参数进行比较。 所有测量技术都是非接触式和非破坏性的，允许它们在晶片制造过程中或之后的任何时间在经处理的半导体衬底上进行。 在第一实施例中，测量振动电极和半导体衬底之间的接触电位差VCPD，同时振动电极下方的半导体衬底经受恒定的高强度照明光束。 VCPD的结果值等于PECVD氧化物层VOX（加常数）之间的电位差。 在第二实施例中，在测量VCPD期间，半导体衬底不被照亮。 常规的SPV装置用于测量半导体衬底的表面势垒电位VSP。 从VCPD的测量值中减去VSP的测量值，得到VOX的值（加一个常数）。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US5894168A Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization 失效
    • Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization
    • 用于制造具有最佳多晶硅互连布局的集成电路的掩模生成技术，用于实现全局平坦化
    • US5894168A
    • 1999-04-13
    • US947521
    • 1997-10-02
    • Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
    • Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
    • H01L21/3105 , H01L21/768 , H01L23/528 , H01L23/48 , H01L23/52 , H01L29/40
    • H01L21/76819 , H01L21/31053 , H01L23/528 , H01L2924/0002
    • A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.
    • 提供了一种光刻掩模衍生方法，用于改善沉积在由衍生的光刻掩模形成的导体上的层间电介质的整体平面性。 衍生出光刻掩模，使得非操作导体彼此间隔开最小距离和与操作导体间隔开的规则间隔排列的导体，其上可使用例如化学机械的电介质层沉积并容易地平坦化 抛光技术。 所得的层间电介质上表面在整个半导体形貌上被全局平坦化到均匀的高度。 操作导体与非操作导体不相似，因为操作导体连接在可操作的集成电路的电路中。 非操作导体不在集成电路路径内连接，并且通常浮动或连接到电源。 因此，非操作导体对集成电路功能没有贡献，而不是为覆盖的层间电介质提供结构平面性。 掩模推导方法适用于金属互连光刻掩模或多晶硅互连光刻掩模。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US06353253B2 Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization 有权
    • Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
    • 由沟槽限定并被氧化物覆盖以改善平坦化的半导体隔离区
    • US06353253B2
    • 2002-03-05
    • US09227914
    • 1999-01-08
    • Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Mark W. Michael , William S. Brennan
    • Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Mark W. Michael , William S. Brennan
    • H01L2900
    • H01L21/76205 , H01L21/76229
    • An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commensurate with the upper surface of adjacent active mesas.
    • 提供隔离技术用于改善隔离区域相对于相邻有源区硅台面的整体平面度。 隔离过程导致在紧邻有源区域的场区域中形成沟槽。 然而，这个沟槽并不完全穿过田野区域。 通过防止大面积沟槽，避免了大量的介电填充材料以及该填充材料随后的平坦化问题。 因此，本发明的隔离技术不需要通常与浅沟槽工艺相关联的常规填充电介质。 虽然它实现了形成硅台面的优点，但是本方法避免了使用常规的牺牲回蚀，块掩模和化学机械抛光在大面积场区域中的电介质表面的返修。 其改进的隔离技术利用在场区周边蚀刻到硅衬底中的最小宽度的沟槽，留下场台面。 在场台面上形成场电介质，优选氧化物，并填充场台面和有源台面之间的沟槽，留下与相邻活性台面的上表面相当的基本上平面的场电介质。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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