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1. 发明授权

US5894168A Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization 失效
标题翻译：用于制造具有最佳多晶硅互连布局的集成电路的掩模生成技术，用于实现全局平坦化
公开(公告)号：US5894168A
公开(公告)日：1999-04-13
申请号：US947521
申请日：1997-10-02
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/3105 , H01L21/768 , H01L23/528 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76819 , H01L21/31053 , H01L23/528 , H01L2924/0002
摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.
摘要翻译：提供了一种光刻掩模衍生方法，用于改善沉积在由衍生的光刻掩模形成的导体上的层间电介质的整体平面性。衍生出光刻掩模，使得非操作导体彼此间隔开最小距离和与操作导体间隔开的规则间隔排列的导体，其上可使用例如化学机械的电介质层沉积并容易地平坦化抛光技术。所得的层间电介质上表面在整个半导体形貌上被全局平坦化到均匀的高度。操作导体与非操作导体不相似，因为操作导体连接在可操作的集成电路的电路中。非操作导体不在集成电路路径内连接，并且通常浮动或连接到电源。因此，非操作导体对集成电路功能没有贡献，而不是为覆盖的层间电介质提供结构平面性。掩模推导方法适用于金属互连光刻掩模或多晶硅互连光刻掩模。

2. 发明授权

US5850105A Substantially planar semiconductor topography using dielectrics and chemical mechanical polish 失效
标题翻译：使用电介质和化学机械抛光的基本平面的半导体形貌
公开(公告)号：US5850105A
公开(公告)日：1998-12-15
申请号：US822120
申请日：1997-03-21
申请人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L23/532 , H01L23/58
CPC分类号： H01L23/5329 , H01L2924/0002
摘要： A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower regions. Subsequent chemical mechanical polishing produces a substantially planar surface.
摘要翻译：一种用于形成具有全局平坦化的上表面的多层互连结构的方法。电介质沉积在半导体上以最小化形貌高度上的先前存在的差异并产生具有比下部区域更高的抛光速率的上表面形貌。随后的化学机械抛光产生基本平坦的表面。

3. 发明授权

US5759913A Method of formation of an air gap within a semiconductor dielectric by solvent desorption 失效
标题翻译：通过溶剂解吸形成半导体电介质内气隙的方法
公开(公告)号：US5759913A
公开(公告)日：1998-06-02
申请号：US658547
申请日：1996-06-05
申请人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L21/283
CPC分类号： H01L21/7682 , H01L21/76828
摘要： A dielectric material is provided having air gaps which form during dielectric deposition between interconnects. The dielectric is deposited in interconnect-spaced geometries which have certain aspect ratios and which are exposed at the bottom of the geometries to a hygroscopic dielectric. During deposition, the dielectric is forced along the sidewall of the spaced interconnects as a result of moisture ougasing from the hygroscopic dielectric. Over a period of time, a keyhole occurs with pile up accumulation (or cusping) at the corners of the spaced interconnects. By decreasing the deposition temperature in a subsequent step, outgasing is minimized, and deposition over the keyhole and upon the hygroscopic dielectric takes place. Keyhole coverage results in an air gap which is surrounded on all sides by the fill dielectric. Air gap between interconnects helps reduce permittivity of the overall dielectric structure, resulting in a lessening of the interconnect line-to-line capacitance.
摘要翻译：提供介电材料，其具有在互连之间的介电沉积期间形成的气隙。电介质沉积在具有特定纵横比的互连隔开的几何形状中，并且在几何形状的底部暴露于吸湿电介质。在沉积期间，电介质由于从吸湿介质的湿气渗出而沿着间隔开的互连件的侧壁被迫。在一段时间内，在间隔互连的角落处堆积积聚（或缩小）时，会产生锁孔。通过在随后的步骤中降低沉积温度，最大限度地减少了沉积，并且在钥匙孔和吸湿介质上沉积。钥匙孔覆盖导致气隙由填充电介质所包围。互连之间的空气间隙有助于降低整个电介质结构的介电常数，导致互连线对线电容的减小。

4. 发明授权

US06353253B2 Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization 有权
标题翻译：由沟槽限定并被氧化物覆盖以改善平坦化的半导体隔离区
公开(公告)号：US06353253B2
公开(公告)日：2002-03-05
申请号：US09227914
申请日：1999-01-08
申请人： Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Mark W. Michael , William S. Brennan
发明人： Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Mark W. Michael , William S. Brennan
IPC分类号： H01L2900
CPC分类号： H01L21/76205 , H01L21/76229
摘要： An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commensurate with the upper surface of adjacent active mesas.
摘要翻译：提供隔离技术用于改善隔离区域相对于相邻有源区硅台面的整体平面度。隔离过程导致在紧邻有源区域的场区域中形成沟槽。然而，这个沟槽并不完全穿过田野区域。通过防止大面积沟槽，避免了大量的介电填充材料以及该填充材料随后的平坦化问题。因此，本发明的隔离技术不需要通常与浅沟槽工艺相关联的常规填充电介质。虽然它实现了形成硅台面的优点，但是本方法避免了使用常规的牺牲回蚀，块掩模和化学机械抛光在大面积场区域中的电介质表面的返修。其改进的隔离技术利用在场区周边蚀刻到硅衬底中的最小宽度的沟槽，留下场台面。在场台面上形成场电介质，优选氧化物，并填充场台面和有源台面之间的沟槽，留下与相邻活性台面的上表面相当的基本上平面的场电介质。

5. 发明授权

US6090703A Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer 有权
标题翻译：形成集成电路的方法，其具有具有蚀刻停止阻挡层的具有增强的横截面面积的导体
公开(公告)号：US6090703A
公开(公告)日：2000-07-18
申请号：US165765
申请日：1998-10-02
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan , Fred N. Hause , Robert Dawson , Mark W. Michael
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan , Fred N. Hause , Robert Dawson , Mark W. Michael
IPC分类号： H01L21/60 , H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76838 , H01L2924/0002
摘要： A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.
摘要翻译：提供具有增强厚度的导体的互连结构。导体包括上部和下部，其中下部几何形状足以增加超过上部提供的载流能力。下部通过在上部电介质区域内填充沟槽而形成，并且通过从直接在下部的正上方的区域除去上电介质表面的导电材料形成上部。上部和下部由此形成增强横截面的导体，其可以通过修改通孔蚀刻掩模而不是必须重新配置和/或移动由金属掩模形成的互连特征而产生。

6. 发明授权

US6031289A Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines 失效
标题翻译：集成电路，其使用凹入的局部导体来产生交错的互连线
公开(公告)号：US6031289A
公开(公告)日：2000-02-29
申请号：US034589
申请日：1998-03-04
申请人： H. Jim Fulford, Jr. , Basab Bandyopadhyay , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Basab Bandyopadhyay , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/316 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L23/522 , H01L27/04 , A07C29/41
CPC分类号： H01L23/5222 , H01L21/768 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.
摘要翻译：提供了一种改进的多级互连结构。互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。在密集间隔的互连区域中，插入的导体被拉至不同的高度级以减小互连之间的电容耦合。通过交错密集图案化区域中的每隔一个互连线，互连能够承载更大量的电流并且在其间具有最小的电容耦合。

7. 发明授权

US5953626A Dissolvable dielectric method 失效
标题翻译：溶解介电法
公开(公告)号：US5953626A
公开(公告)日：1999-09-14
申请号：US659166
申请日：1996-06-05
申请人： Fred N. Hause , Basab Bandyopadhyay , Robert Dawson , H. Jim Fulford, Jr. , Mark W. Michael , William S. Brennan
发明人： Fred N. Hause , Basab Bandyopadhyay , Robert Dawson , H. Jim Fulford, Jr. , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/7682
摘要： A fabrication process that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment of the invention, a first interconnect level is formed on a barrier layer. A temporary support material is then formed over the first interconnect level and a second level of interconnect is formed on the temporary support material. Prior to formation of the second interconnect level, a plurality of pillar openings are formed in the temporary material and filled with a conductive material. In addition to providing a contact between the first and second level of interconnects, the pillars provide mechanical support for the second interconnect level. The temporary material is dissolved in a solution that attacks the temporary material but leaves the interconnect material and pillar material intact. In one embodiment of the invention, a passivation layer is formed on the second interconnect level prior to dissolving the temporary material. The air gap dielectric can be used with more than two levels of interconnect, if desired.
摘要翻译：一种制造气隙电介质的制造工艺，其中在临时支撑材料上形成多层互连结构。随后将临时材料溶解掉，留下由空气组成的层间和层间电介质。在本发明的一个实施例中，在阻挡层上形成第一互连电平。然后在第一互连层上形成临时支撑材料，并在临时支撑材料上形成第二层互连。在形成第二互连级别之前，在临时材料中形成多个柱状开口并填充有导电材料。除了在第一和第二级互连之间提供接触之外，支柱为第二互连电平提供机械支撑。临时材料溶解在攻击临时材料的溶液中，但使互连材料和支柱材料完好无损。在本发明的一个实施例中，在溶解临时材料之前，在第二互连层上形成钝化层。如果需要，气隙电介质可以与多于两个级别的互连一起使用。

8. 发明授权

US5854515A Integrated circuit having conductors of enhanced cross-sectional area 失效
公开(公告)号：US5854515A
公开(公告)日：1998-12-29
申请号：US685143
申请日：1996-07-23
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L23/522 , H01L23/528 , H01L23/52
CPC分类号： H01L23/5226 , H01L23/5283 , H01L2924/0002 , Y10S257/92 , Y10S257/923
摘要： A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.

9. 发明授权

US5854131A Integrated circuit having horizontally and vertically offset interconnect lines 失效
标题翻译：集成电路具有水平和垂直偏移的互连线
公开(公告)号：US5854131A
公开(公告)日：1998-12-29
申请号：US655245
申请日：1996-06-05
申请人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford Jr. , Fred N. Hause , William S. Brennan
发明人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/04 , H01L21/44
CPC分类号： H01L23/5222 , H01L23/5226 , H01L23/5283 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. Accordingly, a space between conductors on one level is directly above or directly below a conductor within another level. The staggered interconnect lines are advantageously used in densely spaced regions to reduce the interlevel and intralevel capacitance. Furthermore, an interlevel and an intralevel dielectric structure includes optimally placed low K dielectrics which exist in critical spaced areas to minimize capacitive coupling and propagation delay problems. The low K dielectric, according to one embodiment, includes a capping dielectric which is used to prevent corrosion on adjacent metallic conductors, and serves as an etch stop when conductors are patterned. The capping dielectric further minimizes the overall intrinsic stress of the resulting intralevel and interlevel dielectric structure.
摘要翻译：提供了一种改进的多级互连结构。互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。因此，在一个级别上的导体之间的空间位于另一层内的导体的正上方或正下方。交错的互连线有利地用于密集间隔的区域以减少层间和层间电容。此外，层间和层间电介质结构包括存在于临界间隔区域中的最佳放置的低K电介质，以最小化电容耦合和传播延迟问题。根据一个实施例的低K电介质包括封盖电介质，其用于防止相邻金属导体上的腐蚀，并且当导体被图案化时用作蚀刻停止层。封盖电介质进一步最小化所得到的层间和层间电介质结构的整体固有应力。

10. 发明授权

US5847462A Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer 失效
标题翻译：集成电路具有具有蚀刻停止阻挡层的具有增强的横截面面积的导体
公开(公告)号：US5847462A
公开(公告)日：1998-12-08
申请号：US748812
申请日：1996-11-14
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan , Fred N. Hause , Robert Dawson , Mark W. Michael
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan , Fred N. Hause , Robert Dawson , Mark W. Michael
IPC分类号： H01L21/60 , H01L21/768 , H01L23/522 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76838 , H01L2924/0002
摘要： An interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.
摘要翻译：提供具有增强厚度的导体的互连结构。导体包括上部和下部，其中下部几何形状足以增加超过上部提供的载流能力。下部通过在上部电介质区域内填充沟槽而形成，并且通过从直接在下部的正上方的区域除去上电介质表面的导电材料形成上部。上部和下部由此形成增强横截面的导体，其可以通过修改通孔蚀刻掩模而不是必须重新配置和/或移动由金属掩模形成的互连特征而产生。

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