专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5894168A Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization 失效
标题翻译：用于制造具有最佳多晶硅互连布局的集成电路的掩模生成技术，用于实现全局平坦化
公开(公告)号：US5894168A
公开(公告)日：1999-04-13
申请号：US947521
申请日：1997-10-02
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/3105 , H01L21/768 , H01L23/528 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76819 , H01L21/31053 , H01L23/528 , H01L2924/0002
摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.
摘要翻译：提供了一种光刻掩模衍生方法，用于改善沉积在由衍生的光刻掩模形成的导体上的层间电介质的整体平面性。衍生出光刻掩模，使得非操作导体彼此间隔开最小距离和与操作导体间隔开的规则间隔排列的导体，其上可使用例如化学机械的电介质层沉积并容易地平坦化抛光技术。所得的层间电介质上表面在整个半导体形貌上被全局平坦化到均匀的高度。操作导体与非操作导体不相似，因为操作导体连接在可操作的集成电路的电路中。非操作导体不在集成电路路径内连接，并且通常浮动或连接到电源。因此，非操作导体对集成电路功能没有贡献，而不是为覆盖的层间电介质提供结构平面性。掩模推导方法适用于金属互连光刻掩模或多晶硅互连光刻掩模。

2. 发明授权

US5850105A Substantially planar semiconductor topography using dielectrics and chemical mechanical polish 失效
标题翻译：使用电介质和化学机械抛光的基本平面的半导体形貌
公开(公告)号：US5850105A
公开(公告)日：1998-12-15
申请号：US822120
申请日：1997-03-21
申请人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L23/532 , H01L23/58
CPC分类号： H01L23/5329 , H01L2924/0002
摘要： A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower regions. Subsequent chemical mechanical polishing produces a substantially planar surface.
摘要翻译：一种用于形成具有全局平坦化的上表面的多层互连结构的方法。电介质沉积在半导体上以最小化形貌高度上的先前存在的差异并产生具有比下部区域更高的抛光速率的上表面形貌。随后的化学机械抛光产生基本平坦的表面。

3. 发明授权

US5759913A Method of formation of an air gap within a semiconductor dielectric by solvent desorption 失效
标题翻译：通过溶剂解吸形成半导体电介质内气隙的方法
公开(公告)号：US5759913A
公开(公告)日：1998-06-02
申请号：US658547
申请日：1996-06-05
申请人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L21/283
CPC分类号： H01L21/7682 , H01L21/76828
摘要： A dielectric material is provided having air gaps which form during dielectric deposition between interconnects. The dielectric is deposited in interconnect-spaced geometries which have certain aspect ratios and which are exposed at the bottom of the geometries to a hygroscopic dielectric. During deposition, the dielectric is forced along the sidewall of the spaced interconnects as a result of moisture ougasing from the hygroscopic dielectric. Over a period of time, a keyhole occurs with pile up accumulation (or cusping) at the corners of the spaced interconnects. By decreasing the deposition temperature in a subsequent step, outgasing is minimized, and deposition over the keyhole and upon the hygroscopic dielectric takes place. Keyhole coverage results in an air gap which is surrounded on all sides by the fill dielectric. Air gap between interconnects helps reduce permittivity of the overall dielectric structure, resulting in a lessening of the interconnect line-to-line capacitance.
摘要翻译：提供介电材料，其具有在互连之间的介电沉积期间形成的气隙。电介质沉积在具有特定纵横比的互连隔开的几何形状中，并且在几何形状的底部暴露于吸湿电介质。在沉积期间，电介质由于从吸湿介质的湿气渗出而沿着间隔开的互连件的侧壁被迫。在一段时间内，在间隔互连的角落处堆积积聚（或缩小）时，会产生锁孔。通过在随后的步骤中降低沉积温度，最大限度地减少了沉积，并且在钥匙孔和吸湿介质上沉积。钥匙孔覆盖导致气隙由填充电介质所包围。互连之间的空气间隙有助于降低整个电介质结构的介电常数，导致互连线对线电容的减小。

4. 发明授权

US06376330B1 Dielectric having an air gap formed between closely spaced interconnect lines 失效
标题翻译：电介质具有形成在紧密间隔的互连线之间的气隙
公开(公告)号：US06376330B1
公开(公告)日：2002-04-23
申请号：US08655242
申请日：1996-06-05
申请人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L2176
CPC分类号： H01L21/7682
摘要： A dielectric material is provided having air gaps purposely formed within the dielectric. The dielectric is deposited, and air gaps formed, between respective interconnect lines. The geometries between interconnect lines is purposely controlled to achieve a large aspect ratio necessary to produce air gaps during CVD of the dielectric. Air gaps exist between interconnects to reduce the line-to-line capacitance, and thereby reduce the propagation delay associated with closely spaced interconnects.
摘要翻译：提供一种电介质材料，其具有在电介质中有目的地形成的气隙。电介质被沉积，并且在相应的互连线之间形成气隙。有意地控制互连线之间的几何形状以实现在电介质CVD期间产生气隙所需的大的纵横比。互连之间存在空隙，以减少线间电容，从而减少与紧密间隔的互连相关的传播延迟。

5. 发明授权

US6127719A Subfield conductive layer and method of manufacture 失效
标题翻译：子场导电层及其制造方法
公开(公告)号：US6127719A
公开(公告)日：2000-10-03
申请号：US038464
申请日：1998-03-11
申请人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/74 , H01L29/00 , H01L31/119
CPC分类号： H01L21/74
摘要： A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.
摘要翻译：提供了一个子场导电层，其中将导电层注入到场电介质的下面和横向附近。在形成场电介质之后，将子场导电层置于硅衬底内。导电层表示驻留在隔离器件之间的掩埋互连。然而，埋入式互连通过使用由LOCOS或浅沟槽隔离技术形成的场电介质的高能离子注入形成。埋置的互连或导电层驻留并电连接两个隔离器件的源极和漏极区域。

6. 发明授权

US5968843A Method of planarizing a semiconductor topography using multiple polish pads 失效
标题翻译：使用多个抛光垫平面化半导体形貌的方法
公开(公告)号：US5968843A
公开(公告)日：1999-10-19
申请号：US768278
申请日：1996-12-18
申请人： Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/3105 , H01L21/302
CPC分类号： H01L21/31053
摘要： An improved method for planarizing an interlevel dielectric comprising two chemical mechanical polish steps. After an interlevel dielectric containing a topographical valley between a pair of topographical peaks is formed, the dielectric is chemically-mechanically polished in a first polish step at a first force using a first polish pad having a first rigidity to round the sharp dielectric corners or edges that exist at the transition between the peaks and valleys. After the first polish step has rounded the edges, a second polish step is performed with a second polish pad of second rigidity. The second polish pad is more rigid than the first polish pad and the second force is greater than the first. The second polish steps uses a high viscosity slurry to reduce slurry turnover in the regions proximate to the dielectric valleys thereby reducing the chemical etching in the valleys and improving the planarization efficiency.
摘要翻译：一种用于平坦化层间电介质的改进方法，包括两个化学机械抛光步骤。在形成包含一对形貌峰之间的形貌谷的层间电介质之后，使用具有第一刚性的第一抛光垫在第一抛光步骤中以第一力进行化学机械抛光的电介质以使尖锐的电介质拐角或边缘存在于峰谷之间的过渡处。在第一抛光步骤使边缘变圆之后，用第二刚性的第二抛光垫进行第二抛光步骤。第二抛光垫比第一抛光垫更刚性，第二抛光垫大于第一抛光垫。第二抛光步骤使用高粘度浆料来减少靠近电介质谷的区域中的浆料周转，从而减少了谷中的化学蚀刻并提高了平坦化效率。

7. 发明授权

US5783864A Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect 失效
公开(公告)号：US5783864A
公开(公告)日：1998-07-21
申请号：US655248
申请日：1996-06-05
申请人： Robert Dawson , Mark W. Michael , William S. Brennan , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause
发明人： Robert Dawson , Mark W. Michael , William S. Brennan , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause
IPC分类号： H01L21/768 , H01L23/522 , H01L29/41
CPC分类号： H01L23/5226 , H01L21/7682 , H01L21/76885 , H01L23/5222 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by air from one another. Furthermore, each conductor within one level of interconnect is spaced by air from each conductor within another level of interconnect. Air gaps afford a smaller interlevel and intralevel capacitance within the multilevel interconnect structure, and a smaller parasitic capacitance value affords minimal propagation delay and cross-coupling noise of signals sent through the conductors. The air gaps are formed by dissolving a sacrificial dielectric, and the conductors are prevented from bending or warping in regions removed of sacrificial dielectric by employing anodization on not just the upper surfaces of each conductor, but the sidewalls as well. The upper and sidewall anodization provides a more rigid metal conductor structure than if merely the upper or sidewall surfaces were anodized. Accordingly, the pillars can be spaced further apart and yet provide all necessary support to the overlying conductors.

8. 发明授权

US5767000A Method of manufacturing subfield conductive layer 失效
标题翻译：制造子场导电层的方法
公开(公告)号：US5767000A
公开(公告)日：1998-06-16
申请号：US655243
申请日：1996-06-05
申请人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/74 , H01L21/76
CPC分类号： H01L21/74
摘要： A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.
摘要翻译：提供了一个子场导电层，其中将导电层注入到场电介质的下面和横向附近。在形成场电介质之后，将子场导电层置于硅衬底内。导电层表示驻留在隔离器件之间的掩埋互连。然而，埋入式互连通过使用由LOCOS或浅沟槽隔离技术形成的场电介质的高能离子注入形成。埋置的互连或导电层驻留并电连接两个隔离器件的源极和漏极区域。

9. 发明授权

US06353253B2 Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization 有权
标题翻译：由沟槽限定并被氧化物覆盖以改善平坦化的半导体隔离区
公开(公告)号：US06353253B2
公开(公告)日：2002-03-05
申请号：US09227914
申请日：1999-01-08
申请人： Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Mark W. Michael , William S. Brennan
发明人： Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Mark W. Michael , William S. Brennan
IPC分类号： H01L2900
CPC分类号： H01L21/76205 , H01L21/76229
摘要： An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commensurate with the upper surface of adjacent active mesas.
摘要翻译：提供隔离技术用于改善隔离区域相对于相邻有源区硅台面的整体平面度。隔离过程导致在紧邻有源区域的场区域中形成沟槽。然而，这个沟槽并不完全穿过田野区域。通过防止大面积沟槽，避免了大量的介电填充材料以及该填充材料随后的平坦化问题。因此，本发明的隔离技术不需要通常与浅沟槽工艺相关联的常规填充电介质。虽然它实现了形成硅台面的优点，但是本方法避免了使用常规的牺牲回蚀，块掩模和化学机械抛光在大面积场区域中的电介质表面的返修。其改进的隔离技术利用在场区周边蚀刻到硅衬底中的最小宽度的沟槽，留下场台面。在场台面上形成场电介质，优选氧化物，并填充场台面和有源台面之间的沟槽，留下与相邻活性台面的上表面相当的基本上平面的场电介质。

10. 发明授权

US6090703A Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer 有权
标题翻译：形成集成电路的方法，其具有具有蚀刻停止阻挡层的具有增强的横截面面积的导体
公开(公告)号：US6090703A
公开(公告)日：2000-07-18
申请号：US165765
申请日：1998-10-02
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan , Fred N. Hause , Robert Dawson , Mark W. Michael
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan , Fred N. Hause , Robert Dawson , Mark W. Michael
IPC分类号： H01L21/60 , H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76838 , H01L2924/0002
摘要： A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.
摘要翻译：提供具有增强厚度的导体的互连结构。导体包括上部和下部，其中下部几何形状足以增加超过上部提供的载流能力。下部通过在上部电介质区域内填充沟槽而形成，并且通过从直接在下部的正上方的区域除去上电介质表面的导电材料形成上部。上部和下部由此形成增强横截面的导体，其可以通过修改通孔蚀刻掩模而不是必须重新配置和/或移动由金属掩模形成的互连特征而产生。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式